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(78)
Edward J. Mccluskey
18
Abhijit Jas
14
C. V. Krishna
13
Kedarnath J. Balakrishnan
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Bahram Pouya
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Authors
Nur A. Touba
Nur A. Touba,University of Texas Austin,Hardware & Architecture,Software Engineering,Engineering
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Nur A. Touba
University of Texas Austin
Publications:
148
|
Citations:
3287
Fields:
Hardware & Architecture
,
Software Engineering
,
Engineering
View FAQ about top research areas and Fields of study
Collaborated with
78 co-authors
from 1993 to 2012
|
Cited by
1942 authors
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Annual
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Publications
(148)
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Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis
Joon-Sung Yang
,
Nur A. Touba
Journal:
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
, vol. 31, no. 3, pp. 442-446, 2012
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories
Rudrajit Datta
,
Nur A. Touba
Conference:
IEEE VLSI Test Symposium - VTS
, pp. 134-139, 2011
X-Stacking - A Method for Reducing Control Data for Output Compaction
Rudrajit Datta
,
Nur A. Touba
Conference:
Defect and Fault Tolerance in VLSI Systems - DFT
, pp. 332-338, 2011
Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes -- A Graph Theoretic Approach
Rudrajit Datta
,
Nur A. Touba
Conference:
Defect and Fault Tolerance in VLSI Systems - DFT
, pp. 367-373, 2011
Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches
(
Citations: 1
)
Rudrajit Datta
,
Nur A. Touba
Conference:
International Test Conference - ITC
, pp. 1-7, 2010
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Citations
(3287 times by 1878 publications)
Matrix Codes for Reliable and Cost Efficient Memory Chips
(
Citations: 3
)
Costas Argyrides
,
Dhiraj K. Pradhan
,
Taskin Koçak
Journal:
IEEE Transactions on Very Large Scale Integration Systems - VLSI
, vol. 19, no. 3, pp. 420-428, 2011
Modeling and Mitigating Transient Errors in Logic Circuits
(
Citations: 3
)
Ilia Polian
,
John P. Hayes
,
Sudhakar M. Reddy
,
Bernd Becker
Journal:
IEEE Transactions on Dependable and Secure Computing - TDSC
, vol. 8, no. 4, pp. 537-547, 2011
On evaluating signal selection algorithms for post-silicon debug
(
Citations: 1
)
Eddie Hung
,
Steven J. E. Wilton
Conference:
International Symposium on Quality Electronic Design - ISQED
, pp. 290-296, 2011
On-chip dynamic signal sequence slicing for efficient post-silicon debugging
(
Citations: 1
)
Yeonbok Lee
,
Takeshi Matsumoto
,
Masahiro Fujita
Conference:
Asia and South Pacific Design Automation Conference - ASP-DAC
, pp. 719-724, 2011
Analysis of SET Effects in a PIC Microprocessor for Selective Hardening
(
Citations: 1
)
Luis Entrena
,
Almudena Lindoso
,
Mario García Valderas
,
Marta Portela
,
Celia López Ongil
Journal:
IEEE Transactions on Nuclear Science - IEEE TRANS NUCL SCI
, vol. 58, no. 3, pp. 1078-1085, 2011
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