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Co-authors
(20)
Ganesh Venkatesh
25
Mahesh Mehendale
16
Rubin A. Parekhji
7
Sandeep Pagey
4
Ajay Khoche
2
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Authors
Sunil D. Sherlekar
Sunil D. Sherlekar,ERNET India,Hardware & Architecture,Software Engineering,Electrical & Electronic Engineering
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Sunil D. Sherlekar
ERNET India
Publications:
35
|
Citations:
265
Fields:
Hardware & Architecture
,
Software Engineering
,
Electrical & Electronic Engineering
View FAQ about top research areas and Fields of study
Collaborated with
20 co-authors
from 1988 to 2003
|
Cited by
336 authors
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Publications
(35)
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A Global Access Independent Billing Model: Users' Perspective
Sunil Sherlekar
,
Rajeev R. Prasad
Journal:
Wireless Personal Communications - WIREL PERS COMMUN
, vol. 26, no. 2, pp. 169-178, 2003
A Global Access Independent Billing Model: Users' Perspective
SUNIL SHERLEKAR
,
RAJEEV R. PRASAD
Published in 2003.
Power Reduction Techniques for Portable DSP Applications
Mahesh Mehendale
,
Sunil D. Sherlekar
Conference:
VLSI Design
, pp. 3-3, 2000
Low Power Code Generation of Multiplication-free Linear Transforms
(
Citations: 1
)
Mahesh Mehendale
,
Sunil D. Sherlekar
Conference:
VLSI Design
, pp. 42-47, 1999
Low-power realization of FIR filters on programmable DSPs
(
Citations: 25
)
Mahesh Mehendale
,
Sunil D. Sherlekar
,
G. Venkatesh
Journal:
IEEE Transactions on Very Large Scale Integration Systems - VLSI
, vol. 6, no. 4, pp. 546-553, 1998
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Citations
(265 times by 220 publications)
A New Subexpression Elimination Algorithm Using Zero-Dominant Set
Firas Al-Hasani
,
Michael Hayes
,
Andrew Bainbridge-Smith
Conference:
Workshop on Electronic Design, Test and Applications - DELTA
, 2011
Efficient coefficient partitioning for decomposed DA-based inner-product computation
Yu Pan
,
Pramod Kumar Meher
Conference:
IEEE International Symposium on Circuits and Systems - ISCAS
, pp. 406-409, 2011
New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter
(
Citations: 2
)
Pramod Kumar Meher
Journal:
IEEE Transactions on Circuits and Systems I-regular Papers - IEEE TRANS CIRCUIT SYST-I
, vol. 57, no. 3, pp. 592-603, 2010
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
(
Citations: 2
)
Andrés Otero
,
Eduardo de la Torre
,
Teresa Riesgo
,
Yana Esteves Krasteva
Conference:
Field-Programmable Logic and Applications - FPL
, pp. 70-76, 2010
Generic Systolic Array for Run-Time Scalable Cores
(
Citations: 2
)
Andrés Otero
,
Yana Esteves Krasteva
,
Eduardo de la Torre
,
Teresa Riesgo
Conference:
Applied Reconfigurable Computing - ARC
, pp. 4-16, 2010
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