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Ram K. Krishnamurthy

Ram K. Krishnamurthy,Intel Corporation,Hardware & Architecture,Electrical & Electronic Engineering,Energy

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Ram K. Krishnamurthy

Intel Corporation

Publications: 118 | Citations: 913

Fields: Hardware & Architecture, Electrical & Electronic Engineering, Energy

Collaborated with 112 co-authors from 1995 to 2012 | Cited by 1302 authors

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Publications (118)

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A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS

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Conference: Solid-State Circuits IEEE International Conference - ISSCC , pp. 184-186, 2012

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

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Conference: Solid-State Circuits IEEE International Conference - ISSCC , pp. 182-184, 2012

A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS

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Conference: Solid-State Circuits IEEE International Conference - ISSCC , pp. 178-180, 2012

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors (Citations: 2)

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Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 46, no. 4, pp. 767-776, 2011

A Robust Edge Encoding Technique for Energy-Efficient MultiCycle Interconnect (Citations: 1)

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Journal: IEEE Transactions on Very Large Scale Integration Systems - VLSI , vol. 19, no. 2, pp. 264-273, 2011

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Citations (913 times by 701 publications)

Model and physical implementation of multi-port PUF in 65 nm CMOS

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Journal: International Journal of Electronics - INT J ELECTRON , vol. ahead-of-p, no. ahead-of-p, pp. 1-14, 2012

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors (Citations: 2)

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Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 46, no. 4, pp. 767-776, 2011

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers (Citations: 2)

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Journal: IEEE Transactions on Very Large Scale Integration Systems - VLSI , vol. 19, no. 7, pp. 1136-1146, 2011

Reliability and Process-variation aware design of integrated circuits — A broader perspective (Citations: 1)

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Published in 2011.

A Robust Edge Encoding Technique for Energy-Efficient MultiCycle Interconnect (Citations: 1)

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Journal: IEEE Transactions on Very Large Scale Integration Systems - VLSI , vol. 19, no. 2, pp. 264-273, 2011

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Co-authors (112)

Conferences (19)

Journals (7)

Keywords (158)

Ram K. Krishnamurthy,Intel Corporation,Hardware & Architecture,Electrical & Electronic Engineering,Energy

Publications (118)

BibTeX | RIS | RefWorks Download

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors (Citations: 2)

A Robust Edge Encoding Technique for Energy-Efficient MultiCycle Interconnect (Citations: 1)

Citations (913 times by 701 publications)

Model and physical implementation of multi-port PUF in 65 nm CMOS

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors (Citations: 2)

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers (Citations: 2)

Reliability and Process-variation aware design of integrated circuits — A broader perspective (Citations: 1)

A Robust Edge Encoding Technique for Energy-Efficient MultiCycle Interconnect (Citations: 1)


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Ram K. Krishnamurthy,Intel Corporation,Hardware & Architecture,Electrical & Electronic Engineering,Energy

Publications (118) BibTeX | RIS | RefWorks Download

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors (Citations: 2)

A Robust Edge Encoding Technique for Energy-Efficient MultiCycle Interconnect (Citations: 1)

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors (Citations: 2)

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers (Citations: 2)

Reliability and Process-variation aware design of integrated circuits — A broader perspective (Citations: 1)

A Robust Edge Encoding Technique for Energy-Efficient MultiCycle Interconnect (Citations: 1)

Publications (118)

BibTeX | RIS | RefWorks Download