Naofumi Takagi

Co-authors (113)

Conferences (19)

Journals (11)

Keywords (129)

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Naofumi Takagi

Naofumi Takagi

Nagoya University

Publications: 86 | Citations: 912 | G-Index: 29 | H-Index: 14

Interests: Hardware & Architecture, Networks & Communications, Electrical & Electronic Engineering

Collaborated with 113 co-authors from 1985 to 2011; Cited by 1116 authors

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Publications (86)

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Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi

Journal: Ieice Transactions - IEICE , vol. 94-C, no. 3, pp. 288-295, 2011
100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process (Citations: 2)

Yuki YAMANASHI, Toshiki KAINUMA, Nobuyuki YOSHIKAWA, Irina KATAEVA, Hiroyuki AKAIKE, Akira FUJIMAKI, Masamitsu TANAKA, Naofumi TAKAGI, Shuichi NAGASAWA, Mutsuo HIDAKA

Journal: Ieice Transactions - IEICE , vol. E93-C, no. 4, pp. 440-444, 2010
100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm

Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka

Journal: Ieice Transactions - IEICE , vol. 93-C, no. 4, pp. 440-444, 2010
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm

Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki

Journal: Ieice Transactions - IEICE , vol. 93-C, no. 4, pp. 435-439, 2010
A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier

Nobutaka Kito, Kensuke Hanai, Naofumi Takagi

Journal: Ieice Transactions - IEICE , vol. 93-D, no. 10, pp. 2783-2791, 2010

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Citations (912 times by 770 publications)

Composite Iterative Algorithm and Architecture for q-th Root Calculation (Citations: 1)

Alvaro V´zquez, Javier D. Bruguera

Conference: IEEE Symposium on Computer Arithmetic - ARITH , pp. 52-61, 2011
Concurrent Error Detection Adder Based on Two Paths Output Computation

Chiraz Khedhiri, Mouna Karmani, Belgacem Hamdi, Ka Lok Man

Conference: IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops - ISPAW , 2011
Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10kA/cm$^{2}$ Nb Process

Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi, Shuichi Nagasawa

Journal: IEEE Transactions on Applied Superconductivity - IEEE TRANS APPL SUPERCONDUCT , vol. 21, no. 3, pp. 827-830, 2011
Architecture and FPGA implementation of the CORDIC algorithm for fingerprints recognition systems

Nihel Neji, Anis Boudabous, Wajdi Kharrat, Nouri Masmoudi

Conference: International Multi-Conference on Systems, Signals and Devices, IEEE - SSD , 2011
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit

Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee

Conference: IEEE International Symposium on Circuits and Systems - ISCAS , pp. 713-716, 2011

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