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Co-authors
(41)
Sung Kyu Lim
8
Dae Hyun Kim
4
Mohit Pathak
3
David Z. Pan (潘志刚)
3
Jae-Seok Yang
3
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(8)
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2
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Academic
Authors
Krit Athikulwongse
Krit Athikulwongse,Georgia Institute of Technology,Hardware & Architecture,Engineering
Edit
Krit Athikulwongse
Georgia Institute of Technology
Publications:
11
|
Citations:
46
Fields:
Hardware & Architecture
,
Engineering
View FAQ about top research areas and Fields of study
Collaborated with
41 co-authors
from 1997 to 2012
|
Cited by
107 authors
Cumulative
Annual
Sort by:
Publications
(11)
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RefWorks
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3D-MAPS: 3D Massively parallel processor with stacked memory
Dae Hyun Kim
,
Krit Athikulwongse
,
Michael Healy
,
Mohammad Hossain
,
Moongon Jung
,
Ilya Khorosh
,
Gokul Kumar
,
Young-Joon Lee
,
Dean Lewis
,
Tzu-Wei Lin
,
Chang Liu
,
Shreepad Panth
http://academic.research.microsoft.com/io.ashx?type=5&id=56953657&selfId1=3340002&selfId2=0&maxNumber=12&query=
Conference:
Solid-State Circuits IEEE International Conference - ISSCC
, pp. 188-190, 2012
Design for manufacturability and reliability for TSV-based 3D ICs
David Z. Pan
,
Sung Kyu Lim
,
Krit Athikulwongse
,
Moongon Jung
,
Joydeep Mitra
,
Jiwoo Pak
,
Mohit Pathak
,
Jae-seok Yang
Conference:
Asia and South Pacific Design Automation Conference - ASP-DAC
, pp. 750-755, 2012
Backend low-k TDDB chip reliability simulator
Muhammad Bashir
,
Dae Hyun Kim
,
Krit Athikulwongse
,
Sung Kyu Lim
,
Linda Milor
Published in 2011.
TSV stress aware timing analysis with applications to 3DIC layout optimization
(
Citations: 11
)
Jae-Seok Yang
,
Krit Athikulwongse
,
Young-Joon Lee
,
Sung Kyu Lim
,
David Z. Pan
Conference:
Design Automation Conference - DAC
, pp. 803-806, 2010
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
(
Citations: 5
)
Michael B. Healy
,
Krit Athikulwongse
,
Rohan Goel
,
Mohammad M. Hossain
,
Dae Hyun Kim
,
Young-Joon Lee
,
Dean L. Lewis
,
Tzu-Wei Lin
,
Chang Liu
,
Moongon Jung
,
Brian Ouellette
,
Mohit Pathak
http://academic.research.microsoft.com/io.ashx?type=5&id=50964663&selfId1=3340002&selfId2=0&maxNumber=12&query=
Conference:
Custom Integrated Circuits Conference - CICC
, pp. 1-4, 2010
Sort by:
Citations
(46 times by 41 publications)
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
(
Citations: 1
)
Moongon Jung
,
Joydeep Mitra
,
David Z. Pan
,
Sung Kyu Lim
Published in 2011.
Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs
(
Citations: 1
)
Xin Zhao
,
Jacob Minz
,
Sung Kyu Lim
Published in 2011.
Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling
(
Citations: 1
)
Dae Hyun Kim
,
Saibal Mukhopadhyay
,
Sung Kyu Lim
Published in 2011.
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Yibo Chen
,
Eren Kursun
,
Dave Motschman
,
Charles Johnson
,
Yuan Xie
Conference:
International Symposium on Low Power Electronics and Design - ISLPED
, pp. 397-402, 2011
Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system
Tao Zhang
,
Po-Yang Hsu
,
Wei-Heng Lo
,
Shau-Yin Tseng
,
Yi-Ta Wu
,
Chuan-Nan Liu
,
Jen-Chieh Yeh
,
Tingting Hwang
,
Yuan Xiel
Conference:
Midwest Symposium on Circuits and Systems - MWSCAS
, pp. 1-4, 2011
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