Co-authors (233)

Conferences (38)

Journals (12)

IEICE

23
VLSI

1
IJEB

1
IJMC

1
PNAS

1

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Masahiko Yoshimoto

Masahiko Yoshimoto,Kobe University,Hardware & Architecture,Networks & Communications,Electrical & Electronic Engineering

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Masahiko Yoshimoto

Kobe University

Publications: 134 | Citations: 199

Fields: Hardware & Architecture, Networks & Communications, Electrical & Electronic Engineering

Collaborated with 233 co-authors from 1997 to 2012 | Cited by 384 authors

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Publications (134)

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A 40-nm 256Kb Sub10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

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Published in 2012.

Bit error rate estimation in SRAM considering temperature fluctuation

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Conference: International Symposium on Quality Electronic Design - ISQED , pp. 516-519, 2012

A 40-nm 256Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367mV VDDmin reduction

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Conference: International Symposium on Quality Electronic Design - ISQED , pp. 489-492, 2012

A variation-aware 0.57-V set-associative cache with mixed associativity using 7T/14T SRAM

, , , ,

Conference: Faible Tension Faible Consommation - FTFC , 2012

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000Word Real-Time Continuous Speech Recognition (Citations: 1)

, , , , ,

Journal: Ieice Transactions - IEICE , vol. 94-C, no. 4, pp. 458-467, 2011

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Citations (199 times by 148 publications)

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM (Citations: 1)

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Conference: International Symposium on Quality Electronic Design - ISQED , pp. 219-222, 2011

Variability-aware duty cycle scheduling in long running embedded sensing systems

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Published in 2011.

Effects of BTI during AHTOL on SRAM VMIN

, , , , ,

Published in 2011.

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

, , , , ,

Journal: IEEE Transactions on Circuits and Systems I-regular Papers - IEEE TRANS CIRCUIT SYST-I , vol. 58, no. 6, pp. 1252-1263, 2011

Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array

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Journal: IEEE Transactions on Electron Devices - IEEE TRANS ELECTRON DEVICES , vol. 58, no. 8, pp. 2249-2256, 2011

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Masahiko Yoshimoto,Kobe University,Hardware & Architecture,Networks & Communications,Electrical & Electronic Engineering

Publications (134) BibTeX | RIS | RefWorks Download

VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000Word Real-Time Continuous Speech Recognition (Citations: 1)

0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM (Citations: 1)

Publications (134)

BibTeX | RIS | RefWorks Download