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Co-authors
(19)
Jonathan Segal
1
K. N. Ratnakumar
1
Shoji Hara
1
Ricardo Ramirez (Ricardo Ramírez)
1
J. D. Kupec
1
Conferences
(2)
ISCAS
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ICWSI
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Academic
Authors
K. Kanegawa
K. Kanegawa,Engineering,Hardware & Architecture
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K. Kanegawa
Publications:
2
|
Citations:
11
Fields:
Engineering
,
Hardware & Architecture
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Collaborated with
19 co-authors
from 1989 to 1990
|
Cited by
16 authors
Cumulative
Annual
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Publications
(2)
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RefWorks
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An overview of BiCMOS technology and applications
(
Citations: 1
)
A. R. Alvarez
,
S. Y. Pai
,
K. N. Ratnakumar
,
G. Gibbs
,
R. Ramirez
,
Y. J. Koh
,
S. T. Robins
,
J. Segal
,
M. J. LaBouff
,
K. Kanegawa
,
R. W. Solfest
,
J. D. Kupec
http://academic.research.microsoft.com/io.ashx?type=5&id=49886227&selfId1=52153686&selfId2=0&maxNumber=12&query=
Conference:
IEEE International Symposium on Circuits and Systems - ISCAS
, 1990
A one megabit SRAM fabricated with 1.2 μ technology
(
Citations: 10
)
B. Warren
,
W. Richardson
,
K. Kanegawa
,
C. Arnell
,
H. Shimizu
,
K. Nakai
,
S. Hara
,
K. Ichiba
Conference:
International Conference on Wafer Scale Integration - ICWSI
, 1989
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Citations
(11 times by 11 publications)
WSI design of a radix 2 butterfly using macrocell pools
Thomas K. Callaway
Conference:
International Conference on Wafer Scale Integration - ICWSI
, 1994
A full experience of designing a wafer scale 2D array
(
Citations: 3
)
A. Boubekeur
,
J. L. Patry
,
G. Saucier
,
M. Slimane-kadi
,
J. Trilhe
Conference:
International Conference on Wafer Scale Integration - ICWSI
, 1993
A real experience on configuring a wafer scale 2D array of monobit processors
Ahmed Boubekeur
,
Jean Luc Patry
,
M. Slimane-Kadi
,
G. Saucier
,
J. Trilhe
Journal:
IEEE Transactions on Components, Hybrids, and Manufacturing Technology
, vol. 16, no. 7, pp. 637-645, 1993
Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors
(
Citations: 9
)
Ahmed Boubekeur
,
Jean-luc Patry
,
Gabriele Saucier
,
Jacques Trilhe
Journal:
IEEE Computer - COMPUTER
, vol. 25, no. 4, pp. 29-39, 1992
Lessons learnt from designing a wafer scale 2D array
(
Citations: 3
)
A. Boubekeur
,
J. L. Patry
,
G. Saucier
,
M. Slimane-kadi
,
J. Trilhe
Conference:
Defect and Fault Tolerance in VLSI Systems - DFT
, 1992
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