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IEEE J SOLID-STATE CIRCUITS

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Marzo Zanuso

Marzo Zanuso,University of California Los Angeles,Electrical & Electronic Engineering

Marzo Zanuso

University of California Los Angeles

Publications: 1 | Citations: 2

Fields: Electrical & Electronic Engineering

Collaborated with 3 co-authors in 2011 | Cited by 11 authors

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Publications (1)

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A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation (Citations: 2)

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Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 46, no. 3, pp. 627-638, 2011

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Citations (2 times by 2 publications)

A 2.9–4.0GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5mW Power (Citations: 1)

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Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 46, no. 12, pp. 2745-2758, 2011

A dither-less all digital PLL for cellular transmitters

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Conference: Custom Integrated Circuits Conference - CICC , pp. 1-8, 2011

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