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Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons

Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons,Clifford E. Cummings,Peter Alfke

Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons   (Citations: 13)
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An interesting technique for doing FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains that are asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. The asynchronous FIFO comparison method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper. To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built- in binary ripple carry logic. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #2) is included. This FIFO design paper builds on information already presented in another FIFO design paper where the FIFO pointers are synchronized into the opposite clock domain before running "FIFO full" or "FIFO empty" tests. The reader may benefit from first reviewing the FIFO Style #1 method before proceeding to this FIFO Style #2 method.
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    • ...Asynchronous FIFO solutions [9], [17] have found a more widespread application in the electronic industry [10] and have become a standard to cross the boundary between different synchronous clock domains, mostly because of design simplicity (compared to pausible clock solutions, they can be designed at RTL and synthesized for any technology [17])...
    • ...Asynchronous FIFO solutions [9], [17] have found a more widespread application in the electronic industry [10] and have become a standard to cross the boundary between different synchronous clock domains, mostly because of design simplicity (compared to pausible clock solutions, they can be designed at RTL and synthesized for any technology [17])...

    Jean-Michel Chablozet al. Lowering the latency of interfaces for rationally-related frequencies

    • ...Specifically, the FIFOs are implemented based on the techniques described in [12] without using any architecture specific components, making IMORC a vendorneutral tool...

    Tobias Schumacheret al. IMORC: Application Mapping, Monitoring and Optimization for High-Perfo...

    • ...In traditional synchronized designs such as asynchronous FIFOs, the latency of the synchronizers directly adds latency to the data, and the number of synchronization stages is set as a trade-off between latency and MTBF [19]...
    • ...Supposing two synchronization stages and taking as a reference the implementation in [19], the worst-case and average latencies of asynchronous FIFOs are respectively 3TR and 2:5TR, which are always higher than the figures of our communication system...

    Jean-Michel Chablozet al. A flexible communication scheme for rationally-related clock frequenci...

    • ...Code and the read/write modules are separated [5] , illustrated as Figure 4. Two clocks (read clock and write clock) are used to drive different modules...

    Yaming Yinet al. Design and implementation of a inter-chip bridge in a Multi-core SoC

    • ...As mention above, Gray code is a discontinuous binary code [6], and has the important property that there is only one different bit between adjacent Gray codes...

    Hualong Zhaoet al. GEMI: A High Performance and High Flexibility Memory Interface Archite...

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