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Fault tolerant and fault testable hardware design

Fault tolerant and fault testable hardware design,P. K. Lala

Fault tolerant and fault testable hardware design   (Citations: 223)
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Published in 1985.
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    • ...Hardware-based fault tolerance is generally implemented exploiting different approaches, as presented in [9], [10], [11] and [13] but all exploiting one or more of the following ideas: − Replication scheme: fault-tolerance is provided by using multiple identical instances of the same system that process the same inputs concurrently, choosing the correct result on the basis of a majority voting mechanism...
    • ...TMR requires more than three times as much hardware as non redundant systems, but it has the advantage that computations can continue without interruption when a fault occurs, moreover no modifications are required to software running in a TMR-equipped computer [13]...

    S. Campagnaet al. A framework to support the design of COTS-based reliable space compute...

    • ...Fault tolerance involves error detection, diagnosis and recovery and affords the ability of a system to continue operation in the presence of faults [1]...

    Ran Biet al. The Diagnostic Dendritic Cell Algorithm for robotic systems

    • ...The conventional two-rail TSC checker module realization is shown in figure 2(a) [4], where (x0, x1) and (y0, y1) are the dual-rail codeword inputs and (e1, e2) are the error signals...
    • ...The conventional gate level realization of a 2-of-4 TSC checker unit is portrayed by figure 3(a) [4], where (x1, x2) and (x3, x4) signify two disjoint code group sets and (z1, z2) represent the error outputs...
    • ...Smith’s cellular realization method [1] is understood to be generally faster [4] [8] compared to Anderson’s [2] or Reddy’s approaches [9] for implementation of m-of-2m checkers of an arbitrary dimension...

    P. Balasubramanianet al. Totally self-checking checker modules revisited

    • ...Generally, the degree of fault tolerance is defined as the maximum number of faults that can be tolerated in the system [9]...

    J. Vialet al. Using TMR Architectures for SoC Yield Improvement

    • ...In order to estimate the effects of multiple faults in the proposed sensor system, Markov model is introduced [6]- [8]...

    Takeshi Kasugaet al. Design of a Highly Safe Model Vehicle for Rear-End Collision Avoidance...

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