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High-Speed DES and Triple DES Encryptor/Decryptor

High-Speed DES and Triple DES Encryptor/Decryptor,Vikram Pasham,Steve Trimberger

High-Speed DES and Triple DES Encryptor/Decryptor   (Citations: 14)
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Summary The future of network security depends on encryption provided in the crucial building blocks, like switches, routers, bridges, and other communication equipment. All broadband applications need high-speed cryptosystems to speed up high-bandwidth data transfers and to protect privacy. DES cryptographic hardware is used to protect civilian satellite communications, gateway servers, set-top boxes, Virtual Private Networks (VPN), video transmissions, and numerous other data transfer applications. An application of DES in VPNs is shown in Figure 1. This application note describes the implementation of high-performance Data Encryption Standard (DES) and Triple DES encryptor/decryptor in Virtex™-II and Virtex-E devices. This implementation operates at 15 Gb/s, making it the fastest encryptor/decryptor available today, surpassing the previous record holder, a custom ASIC (Sandia). This design fits into an XC2V1000 or an XCV400E. Three copies of the DES engine can be combined to triple the bandwidth to 45 Gb/s or to permit Triple-DES encryption at the same data rate, but with additional latency. Application Note: Virtex-E Family and Virtex-II Series
Published in 2001.
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    • ...Cryptographic designers have explored not only realizations on software platforms but at the same time on hardware platforms [1], [3], [7], [10], [12]...
    • ...Similarly in [10] the implementation of highperformance DES and Triple DES algorithms are considered by using Virtex™-II and Virtex-E devices...
    • ...Some approaches improve the theoretical part of DES such as [3] and others improve the DES based on the different implementation approaches such as [1], [10]...
    • ...The last wellknown, fastest and fully pipelined implementation of DES was announced by Xilinx Company in [10] where the modification was on the implementation part and not on the theoretical algorithm of DES...
    • ...The data rate in the fore mentioned design is 15.1 Gbps using VirtexII FPGA platform [10]...
    • ...Various implementations are presented in various platforms for DES algorithm in [1], [3], [4], [9], [10]...
    • ...However, the throughput of current pipelined design is more than the Xilinx one [10] which was 15.1 Gbps...
    • ...Similar to the studies presented in [10], [1], [12], [7], the original implementation of the DES algorithm is considered and the theoretical part is not modified...

    Saeid Taherkhaniet al. Implementation of Non-Pipelined and Pipelined Data Encryption Standard...

    • ...Furthermore, the performance of reconfigurable logic-based systems in many network applications such as encryption [1], compression [2], or network intrusion [3] can sustain the demanding requirements of the payload processing...

    Christoforos Kachriset al. Design and performance evaluation of an adaptive FPGA for network appl...

    • ...Xilinx’s implementation [32] uses a fully pipelined architecture, which allows a very high throughput...

    Xinyu Liet al. An Automatic Design Flow for Data Parallel and Pipelined Signal Proces...

    • ...Furthermore, the performance of reconfigurable logic based systems in many network applications such as encryption [1], compression [2] or network intrusion [3] can sustain the demanding requirements of the payload processing...

    Christoforos Kachriset al. Performance Evaluation of an Adaptive FPGA for Network Applications

    • ...In [17], a TDES implementation in Virtex devices [14] that achieves a throughput of 13.3 Gbps at 207 MHz, is presented...

    Paris Kitsoset al. 64-bit Block ciphers: hardware implementations and comparison analysis

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