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An FPGA for Implementing Asynchronous Circuits

An FPGA for Implementing Asynchronous Circuits,10.1109/MDT.1994.303848,IEEE Design & Test of Computers,Scott Hauck,Steven M. Burns,Gaetano Borriello,C

An FPGA for Implementing Asynchronous Circuits   (Citations: 59)
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Field-programmable gate arrays are a dominant implementation medium for digital circuits, especially for glue logic. Unfortunately, they do not support asynchronous circuits. This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent clocks. We describe Montage, the first FPGA to explicitly support asynchronous circuit implementation, and its mapping software. Montage can be used to realize asynchronous interface circuits or to prototype complete asynchronous systems, thus bringing the benefits of rapid prototyping to asynchronous design. Unfortunately, implementation media for asynchronous circuits and systems have not kept up with those for the synchronous world. Programmable logic devices do not include the special non-digital circuits required by asynchronous design methodologies (e.g., arbiters and synchronizers) nor do they facilitate hazard-free logic implementations. This leads to huge inefficiencies in the implementation of asynchronous designs as circuits require a variety of seperate devices. This has caused most asynchronous designers to focus on custom or semi-custom integrated circuits, thus incurring greater expense in time and money. The net effect has been that optimized and robust asynchronous circuits have not become a part of typical system designs. The asynchronous circuits that must be included are usually designed in an ad-hoc manner with many underlying assumptions. This is a highly error- prone process, and causes implementations to be unnecessarily delicate to delay variations. Field-programmable gate arrays, one of today's dominant media for prototyping and implementing digital circuits, are also inappropriate for constructing more than the simplest asynchronous interfaces. They lack the critical elements at the heart of today's asynchronous designs. Unfortunately, resolving this problem is not just a simple matter of adding these elements to the programmable array. The FPGA must also have predictable routing delay and must not introduce hazards in either the logic or routing. Futhermore, the mapping tools must also be modified to handle asynchronous concerns, especially the proper decomposition of logic to fit into the programmable logic blocks and the proper routing of signals to ensure that required timing relationships are met. Ideally, we need an FPGA that can support both synchronous and asynchronous circuits with comparable efficiency. As a step in this direction we present Montage, an integrated system of FPGA architecture and mapping software designed to support both asynchronous circuits and synchronous interfaces. The architecture provides circuits with hazard-free logic and routing, mutual exclusion elements to handle metastability, and methods for initializing unclocked elements. The mapping software generates placement and signal routing sensitive to the timing demands of asynchronous methods. With these features, the Montage system forms a prototyping and implementation medium for asynchronous designs, providing asynchronous circuits with a powerful tool from the synchronous designer's toolbox.
Journal: IEEE Design & Test of Computers - IEEE D&ToC , vol. 11, no. 3, pp. 60-69, 1994
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    • ...Different styles of asynchronous FPGA architectures were presented since 1992 [5, 18-24] motivated mainly by either low power and/or high speed performance...
    • ...Type-1 (e.g. [18] and [19]) rely on significant elements of timing assumption to guarantee the correctness of the asynchronous logic...

    Hock Soon Lowet al. Variation Tolerant AFPGA Architecture

    • ...There have been 3 main approaches to producing reconfigurable asynchronous circuits: 1) Redesign FPGA architectures specifically for asynchronous logic (and in some cases also synchronous logic [1], [2], [3])...

    Phillip David Fergusonet al. Optimising Self-Timed FPGA Circuits

    • ...Early designs were based on modifying existing synchronous FPGA architectures by adjusting the functional units [4], adding reconfigurable delay lines [5], or replacing the clock by control signals generated by an array of timing cells [6]...

    Khodor Ahmad Fawazet al. A dynamically reconfigurable asynchronous processor for low power appl...

    • ...There have been several attempts to incorporate asynchronous techniques into the design of reconfigurable computers [1] [2] [3]...
    • ...Early designs [1] [2] [3] were based on modifying existing synchronous FPGA architectures by adjusting the functional units [1], adding reconfigurable delay line [2], or replacing the clock by control signals generated by an array of timing cells [3]...
    • ...Early designs [1] [2] [3] were based on modifying existing synchronous FPGA architectures by adjusting the functional units [1], adding reconfigurable delay line [2], or replacing the clock by control signals generated by an array of timing cells [3]...

    Khodor Fawazet al. Conditional Acknowledge Synchronisation in Asynchronous Interconnect S...

    • ...Early designs were based on modifying existing synchronous FPGA architectures by adjusting the functional units [10], adding reconfigurable delay lines [11], or replacing the clock by control signals generated by an array of timing cells [12]...

    Khodor Fawazet al. Implementation of Highly Pipelined Datapaths on a Reconfigurable Async...

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