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An FPGA implementation of a matched filter detector for spread spectrum communications systems

An FPGA implementation of a matched filter detector for spread spectrum communications systems,10.1007/3-540-63465-7_241,T. Mathews,S. G. Gibb,Laurenc

An FPGA implementation of a matched filter detector for spread spectrum communications systems   (Citations: 4)
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The implementation of a matched filter detector (MFD) for use in direct sequence spread spectrum communications is described. First, a brief overview of spread spectrum communications is given, leading to a look at why a matched filter synchronizer is superior to the more commonly used sliding correlator synchronizer. The design requirements for a specific MFD is then given, and the reasons for using an FPGA in this application are examined. Both bit-serial and bit-parallel versions of the circuit were designed. The design process is briefly described and details of individual modules within the design are given. The matched filter detector was implemented in an early Xilinx 4005 FPGA sample. On this older, slower device, the bit-parallel circuit correctly operates with 4-bit input data streams at a rate of 17 MHz; the bit-serial circuit operates at an input rate of 3.4 MHz.
Conference: Field-Programmable Logic and Applications - FPL , pp. 364-373, 1997
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