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AN 8 × 8 RLS BASED MIMO DETECTION ASIC FOR BROADBAND MIMO-OFDM WIRELESS TRANSMISSIONS

AN 8 × 8 RLS BASED MIMO DETECTION ASIC FOR BROADBAND MIMO-OFDM WIRELESS TRANSMISSIONS,Jingming Wang,Babak Daneshrad

AN 8 × 8 RLS BASED MIMO DETECTION ASIC FOR BROADBAND MIMO-OFDM WIRELESS TRANSMISSIONS   (Citations: 1)
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This paper presents the architecture and VLSI implementa- tion of a highly flexible MIMO detection engine which sup- ports a wide array of configurations ranging from 1 × 1 to 8 × 8 square, as well as all possible non-symmetric MIMO configurations. The chip is specifically designed to work with an underlying OFDM modulation scheme, and covers the range of 64 to 1024 subchannels. It implements an RLS based MIMO solution which provides a good balance be- tween hardware complexity and overall system performance (1). To further reduce the complexity frequency domain lin- ear interpolation is also used (2). The actual implementation is based upon the highly scal- able inverse QR decomposition based systolic array archi- tecture (3). A single systolic array is time-multiplexed fo r all OFDM subchannels. This naturally overcomes the pipelin- ing difficulty inherent in traditional single channel systo lic arrays without doubling the array size. In conjunction with the array design, a unique input tagging scheme is incorpo- rated to allow dynamic reconfiguration of the ASIC on a per packet basis, and also to reduce power consumption when only a sub-array is needed for the operation. The final implementation of the MIMO detection en- gine can support configurations as large as 8 × 8 in 12.5 MHz of bandwidth, or a 4 × 4 or any smaller array at up to 25 MHz of bandwidth. The chip was fabricated using a 3.3V/1.8V 0.18μm CMOS technology. The resulting core layout measures 29.2mm2 and clocks at a maximum fre- quency of 58MHz. In 2× 2, 25 MHz configuration, it con- sumes 360mW, whereas in 12.5 MHz, 8 × 8 mode it con- sumes 830mW.
Published in 2006.
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    • ...When applied to a MIMO-OFDM system and combined with the tagging mechanism introduced in [3], this array can be fully pipelined and becomes extremely efficient and versatile in real applications through dynamic reconfiguration for different MIMO settings and channel conditions...
    • ...Since the array is highly reconfigurable, as demonstrated in [3], the latter approach is preferred...
    • ...One such dynamic controlling mechanism of the systolic array can be found in [3]...

    Jingming Wanget al. A Universal Systolic Array for Linear MIMO Detections

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