Memory Built-In Self-Repair
This article describes a word oriented memory test methodology for Built-In Self-Repair (BISR). It contains memory BIST logic, wrapper logic to replace defect words , fuse boxes to store the failing addresses. This allows to use RAMs without spare rows and spare columns used in classic redundancy concepts. Faulty addresses and its expected data will be stored in the redundancy logic immediately after its detection. The BISR simply adds faulty words to the redundancy as long as spare words are available. This avoids unnecessary external or internal redundancy calculation. It is possible to add faulty addresses to faults that have been detected during former runs. The presented memory test allows a memory BISR even if parts of the redundancy is already configured. The fuse box can be connected to a scan register to stream in and out data during test and redundancy configuration. The BISR concept can be described in RTL code. Standard MBIST RTL controllers can be used and adopted to the redundancy wrapper logic. The redundancy and BIST logic is fully synthesizable and can be prepared for reuse. Therefore, it is highly flexible and can be used wit various memory types.