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Ternary computers: part I: motivation for ternary computers

Ternary computers: part I: motivation for ternary computers,10.1145/776378.776392,G. Frieder

Ternary computers: part I: motivation for ternary computers   (Citations: 8)
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In the first part, motivation is presented for a study of Ternary Computers using emulation. Areas of interest and goals of evaluation are briefly outlined.In the second part, a representation of balanced ternary numbers is presented and examined. Microcode is then written to implement parallel operation on these ternary numbers. Results of experiments are reported in order to demonstrate that the goals outlined in Part I can be achieved via emulation.Part I is based on Project MU report 32-72-MU. Part 2 is based on Project MU report 34-72-MU. These reports are not reproduced here in full for sake of brevity.
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    • ...With ternary systems having the benefit of an additional output over their binary counterparts, why did ternary systems fail to thrive? The 20th century saw multiple attempts to design and fabricate digital tri-state logic gates, including the Setun system developed at Moscow State University [13] and the ternac system developed at the State University of New York at Buffalo [14]...

    Christy M. Gearheartet al. DNA-based dynamic logic circuitry

    • ...The theoretical advantages of ternary logic based processing have been extensively researched over the past five decades [3,5,6,8,9,18,19]...

    Primoz Pecaret al. The Ternary Quantum-dot Cellular Automata Memorizing Cell

    • ...The adiabatic clock signal for the tQCA cell is thus based on a sinusoidal function that has been scaled to the interval [0, 1] (see figure 6). After dividing the function into two sections, one monotonically increasing and the other decreasing, we choose the first section as the control signal in the switch phase and the second as the control signal in the release phase...
    • ...In the graph the barrier height is normalized to the interval [0, 1], where value 0 denotes lowered barriers (high probability of the electrons tunnelling between adjacent quantum dots) and value 1 denotes raised barriers (no tunnelling of electrons possible)...

    P. Pecaret al. Adiabatic pipelining: a key to ternary computing with quantum dots

    • ...The potential advantages are greater data storage capabilities, faster arithmetic operations, better support for numerical analysis, non-deterministic and heuristic procedures, communication protocols and e‐cient solving of non-binary problems [1, 2, 3, 4]. Ternary logic is the simplest logic from the set of multi-valued logics and the ternary number system ofiers the most e‐cient way of representing numbers [5]...
    • ...In the graph the barrier height is normalized to the interval [0;1], where value 0 denotes lowered barriers (high probability of the electrons tunnelling between adjacent quantum dots) and value 1 denotes raised barriers (no tunnelling of electrons possible)...
    • ...The adiabatic clock signal for the tQCA cell is thus based on a sinusoidal function that has been scaled to the interval [0;1] (see Fig. 6). Dividing the function into two sections, one monotonically increasing the other decreasing, we choose the flrst section as the control signal in the switch phase and the second as the control signal in the release phase...

    P Pecaret al. Adiabatic pipelining: A key to ternary computing with quantum dots

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