An analytical placer for mixed-size 3D placement

An analytical placer for mixed-size 3D placement,10.1145/1735023.1735044,Jason Cong,Guojie Luo

An analytical placer for mixed-size 3D placement   (Citations: 1)
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Existing 3D placement techniques are mainly used for standard-cell circuits, while mixed-size placement is needed to support high-level functional units and intellectual property (IP) blocks. In this paper we present an analytical 3D placement method that is capable of placing mixed-size circuits. A multiple-stepsize scheme for the analytical solver is proposed to handle standard cells and macros differently for stability and efficiency. To relieve the difficulty of legalization, 3D floorplan-based initial solutions are used to guide the analytical solver. As far as we know, this is the first work that reports 3D placement results for mixed-size circuits. Our experiments show that the multiple-stepsize scheme is better than single-stepsize schemes in both quality and runtime. The experimental results on the ICCAD'04 mixed-size benchmarks show that the 4-tier 3D mixed-size placement can reduce the wirelength by 27% on average compared to 2D placement. The results also show that the 3D mixed-size placement achieves 5.3% shorter wirelength on average than the pseudo 3D placement with similar amount of through-silicon vias (TS vias).
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    • ...There is also an existing work for the mixed-size placement that particularly considers large macros for 3D IC designs [8]...
    • ...(Note that the mixed-size placer [8] is focused more on the handling of big macros and applies the 3D placer [7] for standard-cell placement; for fair comparison, we thus should compare with [7] directly.) The second experiment compared with a recent force-directed 3D placer with TSV area consideration [15]...

    Meng-Kai Hsuet al. TSV-aware analytical placement for 3D IC designs

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