Low power DCT using highly scalable multipliers

Low power DCT using highly scalable multipliers,10.1109/ICIP.2009.5413517,Ricardo Castellanos,Hari Kalva,Ravi Shankar

Low power DCT using highly scalable multipliers  
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Low power consumption in computing systems is a key requirement for devices such as cell phones and cameras. In this paper we present a low power DCT implementation using a highly scalable multiplier. This paper focuses on IDCT with playback applications such as digital photo displays. The proposed solution exploits the fact that the size of the multiplications varies per stage in a multistage IDCT implementation and configuring multipliers to match the needs of each stage saves power. Results are compared with Wallace and array multipliers. We show that using a scalable multiplier and dynamically reconfiguring the width of the multiplier leads to significant power savings (over 72%) with negligible degradation in decoded image quality.
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