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Compensating for variability in FPGAs by re-mapping and re-placement

Compensating for variability in FPGAs by re-mapping and re-placement,10.1109/FPL.2009.5272380,N. Pete Sedcole,Edward A. Stott,Peter Y. K. Cheung

Compensating for variability in FPGAs by re-mapping and re-placement   (Citations: 2)
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Two complementary techniques for reducing the effect of within-die variability on the critical path delay in FPGA circuits are reported. The first technique selects the best LUT mapping from a set of alternative mappings of a logic function for each LUT cluster in the FPGA. The second selects the best assignment of LUTs to physical locations within a cluster. The techniques can be used together, and are shown in Monte Carlo experiments to reduce both the mean and standard deviation of critical path delay.
Conference: Field-Programmable Logic and Applications - FPL , pp. 613-616, 2009
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