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A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding

A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding,10.1007/978-3-642-15696-0_6,Jinjia Zhou,Dajiang Zhou,Gan

A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding  
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In this paper, a bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding component is proposed to save the DRAM traffic. In this component, the motion information including motion vector and reference index, for the co-located picture and the last decoded line, is stored in DRAM. In order to save the DRAM access, a partition based storage format is first applied to condense the MB level data. Then, a DPCM-based variable length coding method is utilized to reduce the data size of each partition. Finally, the total bandwidth is further reduced by combining the co-located and last-line information. Experimental results show that the bandwidth requirement for motion vector calculation can be reduced by 85%~98% on typical 1080p and QFHD sequences, with only 7.8k additional logic gates. This can contribute to near 20% bandwidth reduction for the whole video decoder system.
Conference: IEEE Pacific Rim Conference on Multimedia , pp. 52-61, 2010
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