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On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals

On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals,10.1109/TVLSI.2009.2035322,IEEE Transactions on Very Larg

On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals   (Citations: 1)
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This paper presents a high-performance hybrid test program for software-based self-testing of pipeline processor cores. Experiments on two complex real-life pipeline processors with different gate-level implementations show that the random test program and the deterministic test program can nicely compensate for each other for fault detection. Used together, the hybrid test program achieves good processor fault coverage of more than 98%. This study also develops a test shell to cope with random program execution and interrupt testing. To clarify fault coverage evaluation, this study also presents the concept of micro observation versus macro observation for test responses, showing that the most effective method used for SBST is through a MISR connected to the local bus of the processor.
Journal: IEEE Transactions on Very Large Scale Integration Systems - VLSI , vol. 19, no. 3, pp. 520-524, 2011
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