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Keywords
(9)
Circuit Switched
Design Framework
Design Pattern
Figure of Merit
Network Topology
Statistical Analysis
Use Case
Deep Sub Micron
Power Gating
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Control for Power Gating of Wires
Control for Power Gating of Wires,10.1109/TVLSI.2009.2022269,IEEE Transactions on Very Large Scale Integration Systems,Kris Heyrman,Antonis Papanikola
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Control for Power Gating of Wires
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Kris Heyrman
,
Antonis Papanikolaou
,
Francky Catthoor
,
Peter Veelaert
,
Wilfried Philips
In the deep submicron domain wires consume more power than transistors.
Power Gating
for Wires is a form of bus segmentation that alleviates the power loss from onchip interconnects, by switching off the supply voltage from inactive drivers, cycle by instructioncycle. The success of
Power Gating
for Wires depends much on control: the gain from segmentation can conceivably be undone by control costs. Yet during design exploration, the data required for
statistical analysis
are not available. A theory of efficient control for
Power Gating
for Wires and a design framework, determining the balance of cost factors, at an early stage, are both needed. In this paper, we formulate a theory of Useful State Analysis to obtain minimalredundancy encoding of control information. We establish two figures of merit, based on network topology: Intrinsic Sectioning Gain and Useful Encoding Efficiency. They quantify the power loss reduction achievable, and the success of Useful State Analysis in keeping control costs low. We propose a
design pattern
for the operation of a control plane, wherein the costs of control can be identified. From use cases, we find that architectures can have an Intrinsic Sectioning Gain of 50% and more. Useful Encoding Efficiency is found to be in a range of 4480% for some common multipath architectures. Although ultimately, the limits of feasibility to control
Power Gating
for Wires must be decided by means of statistical analysis, we find Useful State Analysis is applicable to networks with tens of terminals, and that our method of control scales well with increasing network size and complexity.
Journal:
IEEE Transactions on Very Large Scale Integration Systems  VLSI
, vol. 18, no. 9, pp. 12871300, 2010
DOI:
10.1109/TVLSI.2009.2022269
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Citations: 6
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Journal:
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Published in 2003.
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Citations
(1)
Low power finite state machine synthesis using powergating
Sambhu Nath Pradhan
,
M. Tilak Kumar
,
Santanu Chattopadhyay
Journal:
Integration
, vol. 44, no. 3, pp. 175184, 2011