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Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques,10.1109/TVLSI.2009.2037637,IEEE Transactions on Very Large Scale Integra

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques   (Citations: 1)
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As technology scales, the aging effect caused by negative bias temperature instability (NBTI) has become a major reliability concern. In the mean time, reducing leakage power remains to be one of the key design goals. Because both NBTI-in- duced circuit degradation and standby leakage power have a strong dependency on the input vectors, input vector control (IVC) technique could be adopted to reduce the leakage power and mitigate NBTI-induced degradation. The IVC technique, however, is ineffective for larger circuits. Consequently, in this paper, we propose two gate replacement algorithms (direct gate replacement (DGR) algorithm and divide and conquer-based gate replacement (DCBGR) algorithm), together with optimal input vector selection, to simultaneously reduce the leakage power and mitigate NBTI-induced degradation. Our experimental results on 23 benchmark circuits reveal the following. 1) Both DGR and DCBGR algorithms outperform pure IVC technique by 15%-30% with 5% delay relaxation for three different design goals: leakage power reduction only, NBTI mitigation only, and leakage/NBTI cooptimization. 2) The DCBGR algorithm leads to better optimization results and save on average more than 10 runtime compared to the DGR algorithm. 3) The area overhead for leakage reduction is much more than that for NBTI mitigation. Index Terms—Gate replacement, internal node control (INC), leakage power, negative bias temperature instability (NBTI).
Journal: IEEE Transactions on Very Large Scale Integration Systems - VLSI , vol. 19, no. 4, pp. 615-628, 2011
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    • ...Figure 1. Static and dynamic NBTI degradation for different input signal probabilities [7]...
    • ...Instead, Wang et al. [7] proposed fast gate replacement algorithms together with optimal input vector selection to simultaneously reduce NBTI induced circuit degradation and leakage power...
    • ...We adopt the NBTI and leakage co-simulation flow from [7] and add the critical gate calculation from [17] to speed up calculation...
    • ...We implement the gate replacement technique from [7] in 32nm high performance PTM technology [10] in order to make a comparison with the proposed technique...

    Chin-Hung Linet al. TG-based technique for NBTI degradation and leakage optimization

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