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Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates

Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates,10.1587/transele.E93.C.932,Ieice Transactions,Keivan Navi,Fazel Sharifi,Amir Momeni,Pei

Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates  
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In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.
Journal: Ieice Transactions - IEICE , vol. 93-C, no. 6, pp. 932-934, 2010
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