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Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability,10.1109/4.777109,IEEE Journal of Solid-state Circuits,Wei Hwan

Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability   (Citations: 22)
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This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22°C with Vdd=2.5 V) and 300 mW. The adder core size is 1.6×0.275 mm2. The process technology used was the 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs
Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 34, no. 8, pp. 1108-1117, 1999
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