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Keywords
(8)
Circuit Design
Dynamic Logic
High Frequency
Highspeed Integrated Circuits
Indexing Terms
Low Power
Power Dissipation
Propagation Delay
Related Publications
(4)
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Implementation of a selfresetting CMOS 64bit parallel adder with enhanced testability
Implementation of a selfresetting CMOS 64bit parallel adder with enhanced testability,10.1109/4.777109,IEEE Journal of Solidstate Circuits,Wei Hwan
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Implementation of a selfresetting CMOS 64bit parallel adder with enhanced testability
(
Citations: 22
)
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Wei Hwang
,
George Diedrich Gristede
,
Pia Sanda
,
Shao Y. Wang
,
David F. Heidel
This paper presents a fast, lowpower, binary carrylookahead, 64bit dynamic parallel adder architecture for highfrequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by selfresetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal
propagation delay
and
power dissipation
of the adder were measured to be 1.5 ns (at 22°C with Vdd=2.5 V) and 300 mW. The adder core size is 1.6×0.275 mm2. The process technology used was the 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs
Journal:
IEEE Journal of Solidstate Circuits  IEEE J SOLIDSTATE CIRCUITS
, vol. 34, no. 8, pp. 11081117, 1999
DOI:
10.1109/4.777109
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Citation Context
(18)
...
1999
; Ejnioui and Alsharqawi
2004
) uses delay buffers that are required to delay the reset signal long enough to allow the outputs of the combinational network to stabilise...
M. Santhi
,
et al.
Performance analysis of pseudo 4phase dualrail asynchronous protocol
...Though many efforts have been focused on the improvement of adder and multiplier designs, [8, 9, 11], to challenge the GHz operations, the major tradeoff of these GHz logic circuits is the high power consumption which is not a tolerable price to pay in recent mobile technologies [
3
, 10]...
Chuachin Wang
,
et al.
LowPower Multiplier Design Using a Bypassing Technique
...Though many efforts have been focused on the improvement of adder and multiplier designs [1], the major tradeoff of these high speed logic circuits are the high power consumption and high temperature which are not a tolerable price to pay in recent mobile technologies [
2
]...
Gangneng Sung
,
et al.
A poweraware 2dimensional bypassing multiplier using cellbased desi...
...Self resetting logic blocks have been reported in the context of RAM designs with very short cycle times [
6
, 7, 8, 9] and, more recently, in wavepipelining [10]...
Amjed AlMousa
,
et al.
Delay faults in dualrail, selfreset wavepipelined circuits
...Although SRSL resembles the selfresetting approach proposed in [
25
], it is quite generic since it is operates at the stage level using static CMOS gates, rather than at the gate level using dynamic circuits...
Abdelhalim Alsharqawi
,
et al.
Clockless Pipelining for Coarse Grain Datapaths
References
(22)
A 64bit carry look ahead adder using pass transistor BiCMOS gates
(
Citations: 13
)
K. Ueda
,
H. Suzuki
,
K. Suda
,
H. Shinohara
,
K. Mashiko
Journal:
IEEE Journal of Solidstate Circuits  IEEE J SOLIDSTATE CIRCUITS
, vol. 31, no. 6, pp. 810818, 1996
A 500MHz, 32word×64bit, eightport selfresetting CMOS register file
(
Citations: 22
)
Wei Hwang
,
Rajiv V. Joshi
,
Walter H. Henkels
Journal:
IEEE Journal of Solidstate Circuits  IEEE J SOLIDSTATE CIRCUITS
, vol. 34, no. 1, pp. 5667, 1999
A 1.0GHz singleissue 64bit powerPC integer processor
(
Citations: 54
)
Joel Silberman
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Naoaki Aoki
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David Boerstler
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,
Axel Essbaum
,
Uttam Ghoshal
,
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,
Peter Hofstee
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Kyung Tek Lee
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David Meltzer
,
Hung Ngo
http://academic.research.microsoft.com/io.ashx?type=5&id=1521776&selfId1=0&selfId2=0&maxNumber=12&query=
Journal:
IEEE Journal of Solidstate Circuits  IEEE J SOLIDSTATE CIRCUITS
, vol. 33, no. 11, pp. 16001608, 1998
Evaluation of three 32bit CMOS adders in DCVS logic for selftimed circuits
(
Citations: 19
)
Gustavo A. Ruiz
Journal:
IEEE Journal of Solidstate Circuits  IEEE J SOLIDSTATE CIRCUITS
, vol. 33, no. 4, pp. 604613, 1998
A 2ns cycle, 3.8ns access 512kb CMOS ECL SRAM with a fully pipelined architecture
(
Citations: 79
)
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Journal:
IEEE Journal of Solidstate Circuits  IEEE J SOLIDSTATE CIRCUITS
, vol. 26, no. 11, pp. 15771585, 1991
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Citations
(22)
Performance analysis of pseudo 4phase dualrail asynchronous protocol
M. Santhi
,
Siddharth Sarangan
,
K. Murali
,
G. Lakshminarayanan
Journal:
International Journal of Electronics  INT J ELECTRON
, vol. aheadofp, no. aheadofp, pp. 113, 2012
LowPower Multiplier Design Using a Bypassing Technique
(
Citations: 7
)
Chuachin Wang
,
Gangneng Sung
Journal:
Journal of Signal Processing Systems  JSPS
, vol. 57, no. 3, pp. 331338, 2009
A poweraware 2dimensional bypassing multiplier using cellbased design flow
(
Citations: 3
)
Gangneng Sung
,
Yanjhin Ciou
,
Chuachin Wang
Conference:
IEEE International Symposium on Circuits and Systems  ISCAS
, pp. 33383341, 2008
Delay faults in dualrail, selfreset wavepipelined circuits
Amjed AlMousa
,
Samiha Mourad
Conference:
Midwest Symposium on Circuits and Systems  MWSCAS
, pp. 13521355, 2007
New Data Encoding Method with a MultiValue Logic for Low Power Asynchronous Circuit Design
(
Citations: 1
)
Eunju Choi
,
Kyoungrok Cho
,
Jehoon Lee
Conference:
IEEE International Symposium on MultipleValued Logic  ISMVL
, pp. 44, 2006