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All-digital PLL and transmitter for mobile phones

All-digital PLL and transmitter for mobile phones,10.1109/JSSC.2005.857417,IEEE Journal of Solid-state Circuits,R. Bogdanstaszewski,J. L. Wallberg,S.

All-digital PLL and transmitter for mobile phones   (Citations: 171)
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R. Bogdanstaszewski, J. L. Wallberg, S. Rezeq, Chih-Ming Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, Meng-Chang Lee, P. Cruisehttp://academic.research.microsoft.com/io.ashx?type=5&id=1526697&selfId1=0&selfId2=0&maxNumber=12&query=
Journal: IEEE Journal of Solid-state Circuits - IEEE J SOLID-STATE CIRCUITS , vol. 40, no. 12, pp. 2469-2482, 2005
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    • ...2005; Kratyuk, Hanumolu, Moon, and Maryaram 2007; McCune 2010)...

    Omar Al-Kharji AL-Aliet al. Digital tanlock loop architecture with no delay

    • ...To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged as an alternative to analog PLLs [1]–[7]...
    • ...For example, an LC-based DCO with excellent phase noise is combined with a very low PLLbandwidthtosuppresstheTDCquantizationerror[1].Very high DCO resolution is achieved by simply limiting the DCO tuning range...

    Wenjing Yinet al. A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With B...

    • ...The DFC consists of the alldigital PLL (ADPLL) [5], which is based on the digitally controlled oscillator (DCO) [6]...
    • ...The resulting ADPLL spectrum is shaped by the loop filter and the noise sources such as the reference, the TDC, and the DCO [5]...
    • ...Fig. 4 shows the linearized s-domain model of a type-II ADPLL [5] with noise sources (reference), (TDC), (DCO), and (AM-FM)...
    • ...The variation of TDC inverter delay [5] over this temperature range is also plotted (red trend line), which will be used to compensate the phase over temperature...

    Imran Bashiret al. A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Tr...

    • ...One of those researches is an all-digital PLL (ADPLL) in which all input-output signals are digital [1]-[5]...
    • ...In the conventional TDC, two asynchronous clocks, CKref (reference clock) and CKV (DCO clock), are employed to estimate the fractional error between the two clocks [1]...
    • ...Since the high-speed DCO clocking application to the TDC increases both dynamic and short current power in the inverter chain, efforts to reduce the inverter input clock speed have been made in various ADPLLs [1]-[5]...
    • ...In [1], also, the two quantized time delays Δtr and Δtf are required to calculate the DCO clock period TV. Therefore, the TV estimation accompanies complex calculation algorithm and more digital gate-level synthesis area...
    • ...While the DCO clock edge counting in an integer precision configuration is not capable of catching the fine phase error below a half CKV cycle, TDC with a time quantization resolution of one inverter delay time tinv can measure that under a half period (sub-Tv), which causes quantization noise due to limited resolution [1]-[5]...
    • ...Unlike the conventional TDC clock scheme [1], the proposed TDC measures the very small time intervals between CKref and pCKR edges instead of that between CKref and CKV...

    Ja-Yol Leeet al. A 4GHz all digital fractional-N PLL with low-power TDC and big phase-e...

    • ...Even though there is no divide-by- in the feedback path, similar to TDC based PLLs [2] or sub-sampling PLLs [21], this noise is multiplied by . Therefore, the reference amplifier needs to be sized large enough so that the noise appears only at the low offset frequency region and does not deteriorate overall phase noise performance...
    • ...The type-II characteristic is preferable since it can provide 40 dB/decade filtering inside of the loop bandwidth and achieves better suppressionontheup-converted noiseoftheDCO[2].TheFIR filter isinsertedtosuppressthequantizationnoisefrom thePDC beyond 20MHzoffset.Thankstothealldigitalimplementation, the filter coefficients are programmable, thus enabling flexible choices for the loop bandwidth...

    Koji Takinamiet al. A Distributed Oscillator Based All-Digital PLL With a 32Phase Embedded...

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