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Efficient one-dimensional systolic array realization of the discrete Fourier transform

Efficient one-dimensional systolic array realization of the discrete Fourier transform,J. a. Beraldin,T. Aboulnasr,W. Steenaart

Efficient one-dimensional systolic array realization of the discrete Fourier transform   (Citations: 25)
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    • ...In the literatures, there are different approaches proposed to implement the 1-D DFT, including the FFT-based designs [1-4] and DFT-based designs [5-11]...
    • ...On the other hand, the DFT-based design [5-11] take advantages of the regular data flow in the DFT algorithm and adopt regular architectures like systolic array, distributed arithmetic architecture, and adder-based architecture to increase the feasibility for VLSI implementation...

    Chih-da Chienet al. A power-aware IP core generator for the one-dimensional discrete Fouri...

    • ...In this paper we use the 1-D DFT array by Beraldin et al. [15] and derive a modular array structure for computing the 2-D DFT without transposition memory...
    • ...2 and 3, except that by using a DFT algorithm known as Goertzel’s DFT [15] we may reduce kernel coefficient storage and simplify control complexity...
    • ...The 1-D DFT array by Beraldin et al. [15] based on the so-called Goertzel Algorithm is derived by applying Horner’s polynomial multiplication rule...
    • ...See Beraldin et al. [15] for a discussion on output pipelining and systolization for the DFT...

    José Fridmanet al. Distributed Memory Parallel Architecture Based on Modular Linear Array...

    • ...Hence, many researchers (Kung, 1980, 1982; Beraldin et al.,1989; Chang and Chen, 1988; Bayoumi et al., 1988; Curtis and Wickenden,1983; Thompson, 1983; Liu and Jen, 1991) have observed that fast Fourier transform (FFT)-like algorithms which have been used extensively due to the small number of multiplications required are not well suited for VLSI implementation...
    • ...Different approaches have been proposed in the literature to implement 1-D DFT designs, including multiplierbased designs (Fang and Wu, 1997; Chang and Chen, 1988; Murthy and Swamy, 1994; Chan and Panchanathan, 1993; Sedukhin, 1994; Gudvangen and Holt, 1990), coordinate rotation digital computer (CORDIC)-based designs (Kocsis, 1991; Wang et al., 1992), read only memory (ROM)-based designs (White, 1989; Beraldin et al., 1989; Guo et al., ...
    • ...sors, ROM-based designs (White, 1989; Beraldin et al., 1989; Guo et al., 1992) are efficient choices for implementing 1-D DFT in certain applications...
    • ...Among the ROM-based designs, the distributed arithmetic (DA)based designs (White, 1989; Beraldin et al., 1989) and the memory-based design (Guo et al., 1992) are two different approaches to realize multiplications using ROMs...
    • ...As illustrated in Chang and Jen (1998), the adder-based designs are more hardware efficient than the ROM-based designs (Beraldin et al., 1989; Guo et al., 1992)...

    JIUN-IN GUO. Efficient parallel adder based design for one-dimensional discrete cos...

    • ...Many of the existing methods of mapping algorithms onto multidimensional systolic architectures are semisystolic [3], [10], which means that 1) the input data must be preloaded into every cell of the array or that 2) the output data is produced throughout the array (i.e., not just at the boundary of the array)...

    Hyesook Lim. Multidimensional systolic arrays for the implementation of discrete Fo...

    • ...A popular approach for these transforms are systolic arrays designs[l][2]...

    Tian-Sheuan Changet al. Hardware efficient transform designs with cyclic formulation and subex...

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