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3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture,10.1016/j.sse.2010.07.019,Solid-state Electronics,Jang-Gn

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3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture   (Citations: 2)
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A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application.
Journal: Solid-state Electronics - SOLID STATE ELECTRON , vol. 55, no. 1, pp. 37-43, 2011
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