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Modeling the "Effective capacitance" for the RC interconnect of CMOS gates

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates,10.1109/43.331409,IEEE Transactions on Computer-aided Design of Integrated

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Modeling the "Effective capacitance" for the RC interconnect of CMOS gates (Citations: 150)


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With finer line widths and faster switching speeds, the resistance of on-chip metal interconnect is having a dominant impact on the timing behavior of logic gates. Specifically, the gates are switching faster and the interconnect delays are getting longer due to scaling. This results in a trend in which the RC interconnect delay is beginning to comprise a larger portion of the overall logic stage delay. This shift in relative delay dominance from the gate to the RC interconnect is increased by resistance shielding. That is, as the gate “resistance” gets smaller and the metal resistance gets larger, the gate no longer “sees” the total net capacitance and the gate delay may be significantly less than expected. This trend complicates the timing analysis of digital circuits, which relies upon simple, empirical gate delay equations for efficiency. In this paper, we develop an analytical expression for the “effective load capacitance” of a pc interconnect. In addition, when there is significant shielding, the response waveforms at the gate output may have a large exponential tail. We show that this waveform tail can strongly influence the delay of the RC interconnect. Therefore, we propose an extension of the effective capacitance equation that captures the complete waveform response accurately, with a two-piece gate-output-waveform approximation

Journal: IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems , vol. 13, no. 12, pp. 1526-1535, 1994

DOI: 10.1109/43.331409

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- ...The wire delays are computed in the static timer with techniques similar to [19] and [20] using resistance and capacitance computed by (4)–(6)...
Eric A. Foreman, et al. Inclusion of Chemical-Mechanical Polishing Variation in Statistical St...
- ...With the resistive component of interconnect becoming comparable to the gate output impedance, modeling of CMOS gate driving resistor-capacitor (RC) line was presented in [5]‐[7]...
Xiao-Chun Li, et al. Transient Analysis of CMOS-Gate-Driven RLGC Interconnects Based on FDT...
- ...This phenomenon is because of the resistive shielding effect [5]...
Chang Liu, et al. Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
- ...Based on the concept of effective capacitance [23], these methods formalize the effect of the interconnect load on the gate driver...
- ...In [21], an extension to the empirical model presented in [23], the -factor empirical fitting technique was introduced where the driving point admittance of the load is accounted for...
- ...The interconnect-dependent gate delay can be explained through the concept of resistance shielding effect [23]...
- ...Qian et al. [23] proposed the model of effective load capacitance for interconnects in order to capture this shielding effect in accurate delay modeling...
- ...One may use (9) as an initial guess to find an accurate value in more complex algorithms [23], [29]...
Myeong-Eun Hwang, et al. Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Mode...
- ...Therefore, equivalent load capacitance at the victim coupling point is less than coupling capacitance and can be formulated using coupling/branching admittance concept [10]...
- ...First tree branches are reduced to a simple π model following the moment matching method as demonstrated in [10]...
Selahattin SAYIL, et al. Accurate Prediction of Crosstalk for RC Interconnects

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Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation (Citations: 1)

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Journal: IEEE Transactions on Circuits and Systems I-regular Papers - IEEE TRANS CIRCUIT SYST-I , vol. 56, no. 7, pp. 1428-1441, 2009

Keywords (4)

Related Publications (17)

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates,10.1109/43.331409,IEEE Transactions on Computer-aided Design of Integrated

Citation Context (100)

Eric A. Foreman, et al. Inclusion of Chemical-Mechanical Polishing Variation in Statistical St...

Xiao-Chun Li, et al. Transient Analysis of CMOS-Gate-Driven RLGC Interconnects Based on FDT...

Chang Liu, et al. Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

Myeong-Eun Hwang, et al. Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Mode...

Selahattin SAYIL, et al. Accurate Prediction of Crosstalk for RC Interconnects

References (11)

Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer (Citations: 30)

Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips (Citations: 20)

Signal Delay in RC Tree Networks (Citations: 509)

Switch-level delay models for digital MOS VLSI (Citations: 71)

Macromodeling CMOS circuits for timing simulation (Citations: 38)

Citations (150)

Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis

Transient Analysis of CMOS-Gate-Driven RLGC Interconnects Based on FDTD

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation (Citations: 1)


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