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Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis,10.1145/1216919.1216949,N. Pete Sedcole,Peter Y. K. Cheung

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis   (Citations: 13)
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Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re-configurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variability. This paper presents three reconfiguration-based strategies for compensating within-die stochastic delay variability in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static timing analysis (SSTA). It is demonstrated that significant im-provements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques.
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