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Information theoretic approach to address delay and reliability in long on-chip interconnects

Information theoretic approach to address delay and reliability in long on-chip interconnects,10.1145/1233501.1233563,Rohit Singhal,Gwan S. Choi,Rabi

Information theoretic approach to address delay and reliability in long on-chip interconnects   (Citations: 5)
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With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, the effects of crosstalk are detrimental to the overall system performance due to the large delays and un-reliability involved. This paper presents an information theoretic approach to address delay and reliability in long interconnects. A framework to calculate the capacity of a physical wire is laid out herein. The results for 8-bit wide buses of varying lengths in 0.1μm technology are also presented. The wires are modeled based on their calculated parasitic (R, L, C) values and the coupling (C, L) parameters. Using this model, results are obtained for the data transfer capacity of long interconnects. It is seen that for wide buses, the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication-theory, these "good" signals arriving early can be used to predict/correct the "few" signals arriving late. Further, results show that for every bus configuration, there exists an optimal frequency of transmission that will result in the maximum data transfer rate. Also, this optimal frequency is higher than the pessimistic worst case delay based clock design.
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    • ...The data-link layer can provide the functional and procedural means to detect and possibly correct errors that may occur in the physical layer, by employing error correcting codes (ECCs) [12, 13, 14], data encoding [15, 16], and redundancy based reconfiguration [17]...

    Cristinel Ababeiet al. Energy and reliability oriented mapping for regular Networks-on-Chip

    • ...It is shown that optimal operation frequency at which the data rate is maximum is 70GHz for an 0.5mm SWCNT bundle interconnects compared to 40GHz for an 0.1µm Cu interconnect technology [4][18]...

    Masud H Chowdhury. Information theoretic capacity analysis of single-walled carbon nanotu...

    • ...Previous works [22], [23] by the authors derives the...
    • ...Reference [22] assumes only capacitive cross-talk, while [23] calculates the data capacity in the presence of both capacitive and inductive cross-talk and also power noise...
    • ...Further, [23] also compares the codes proposed/discussed in [11] against this data capacity...
    • ...The second approach makes use of the Shannon’s capacity theorem like [22] and [23]...
    • ...The small section of an -bit-wide bus can be described as a multi-input–multi-output (MIMO) LTI system [15], [22], [23]...
    • ...These conditions can be broadly classified into the states [22], [23] listed in Table I.2 There are more states compared to [22], because unlike capacitive coupling, which is symmetric from the left and the right neighbor, inductive coupling is asymmetric...

    Rohit Singhalet al. Data Handling Limits of On-Chip Interconnects

    • ...The second approach, discussed in Ch. III, makes use of the Shannon’s capacity theorem like [34,35]...

    ROHIT SINGHAL. DATA INTEGRITY FOR ON-CHIP INTERCONNECTS

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