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A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors,10.1145/1165573.1165593,Pong-fei Lu,Nianzheng Cao,Leo

A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors   (Citations: 1)
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We have reported previously [1] a low-swing latch (LSL) with superior performance-power tradeoff compared to the conventional pass-gate master-slave latch. In this paper, hardware results are presented for the proposed LSL with pulsed clock waveforms. The motivation is to combine low-voltage swing with pulsed signals to further reduce overall system power in high-frequency microprocessors. We have designed a 65-bit accumulator loop experiment to mimic a microprocessor pipeline stage. The local clock buffer design features a mode switch to toggle between two-phase (c1/c2) master-slave clocking and one-phase pulsed (c2 only) clocking. Our data show that 15-25% system power saving can be achieved in pulsed mode compared to non-pulsed mode. Power contribution from individual components is also presented.
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    • ...Typically, the clock power consumed by the sequential elements (flip-flops and latches) and by the local clock buffers driving them is much larger than the power required for global clock distribution [1, 2]. Consequently, several circuit topologies have been proposed to reduce the clock power consumption of the sequential elements...
    • ...It finally explains how the low-swing clocking scheme of [2] can be improved to further reduce the dynamic power consumption of the new latch without degrading its timing...
    • ...In [2], for instance, a separate VDD is dedicated to the local clock buffers and a power reduction of 7% is reported when the latches Table 1: Area...

    Martin Saint-laurentet al. A 65-nm pulsed latch with a single clocked transistor

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