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The FEI4 pixel readout integrated circuit

The FEI4 pixel readout integrated circuit,10.1016/j.nima.2010.04.101,Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrom

The FEI4 pixel readout integrated circuit   (Citations: 3)
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M. Garcia-Sciveres, D. Arutinov, M. Barbero, R. Beccherle, S. Dube, D. Elledge, J. Fleury, D. Fougeron, F. Gensolen, D. Gnani, V. Gromov, T. Hemperekhttp://academic.research.microsoft.com/io.ashx?type=5&id=26423857&selfId1=0&selfId2=0&maxNumber=12&query=
A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.
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