A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA

A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA,10.1109/TNANO.2010.2041555,IEEE Transactions on Nanotechnology,

A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA   (Citations: 1)
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Research efforts to develop a novel memory tech- nology that combines the desired traits of nonvolatility, high en- durance, high speed, and low power have resulted in the emer- gence of spin-torque transfer RAM (STTRAM) as a promising next-generation universal memory. Although industrial efforts have been made to design efficient embedded memory arrays using STTRAM, the prospect of developing a nonvolatile field- programmable gate array (FPGA) framework with STTRAM ex- ploiting its high integration density remains largely unexplored. In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework, identify the key design challenges, and propose opti- mization techniques at circuit, architecture, and application map- ping levels. We show that intrinsic properties of STTRAM that dis- tinguish it from conventional static RAM (SRAM), such as asym- metric readout power, where a cell storing "0" has 5× less read power than a cell storing "1", can be leveraged to skew lookup table contents for FPGA power reduction. We also argue that the proposed framework should operate on static voltage-sensing- based logic evaluation. We identify static power dissipation during logic evaluation and read noise margin as key design concerns and present an optimized resistor-divider design for voltage sensing to reduce static power and noise margin. Finally, we investigate the effectiveness of Shannon-decomposition-based supply gating to reduce static power. Simulation results show improvement of 44.39% in logic area and 22.28% in delay of a configurable logic block (CLB) and average improvement of 16.1% dynamic power over a conventional CMOS FPGA design for a set of benchmark circuits.
Journal: IEEE Transactions on Nanotechnology - IEEE TRANS NANOTECHNOL , vol. 10, no. 3, pp. 385-394, 2011
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    • ...Present FPGA platforms can be broadly divided into two classes: SRAM-based FPGAs (such as Xilinx Virtex), which employ SRAM cells to store the configuration and flash and antifuse-based FPGAs (such as Actel and Quicklogic), which use nonvolatile memory for storing configuration[4]...

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