Analog circuit verification by statistical model checking

Analog circuit verification by statistical model checking,10.1109/ASPDAC.2011.5722168,Ying-Chih Wang,Anvesh Komuravelli,Paolo Zuliani,Edmund M. Clarke

Analog circuit verification by statistical model checking  
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We show how statistical Model Checking can be used for verifying properties of analog circuits. As integrated circuit technologies scale down, manufacturing variations in devices make analog designs behave like stochastic systems. The problem of verifying stochastic systems is often difficult because of their large state space. Statistical Model Checking can be an efficient verification technique for stochastic systems. In this paper, we use sequential statistical techniques and model checking to verify properties of analog circuits in both the temporal and the frequency domain. In particular, randomly sampled system traces are sequentially generated by SPICE and passed to a trace checker to determine whether they satisfy a given specification, until the desired statistical strength is achieved.
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