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The 48-core SCC Processor: the Programmer's View

The 48-core SCC Processor: the Programmer's View,10.1109/SC.2010.53,Timothy G. Mattson,Michael Riepen,Thomas Lehnig,Paul Brett,Werner Haas,Patrick Ken

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The 48-core SCC Processor: the Programmer's View   (Citations: 6)
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The number of cores integrated onto a single die is expected to climb steadily in the foreseeable future. This move to many-core chips is driven by a need to optimize performance per watt. How best to connect these cores and how to program the resulting many-core processor, however, is an open research question. Designs vary from GPUs to cache-coherent shared memory multiprocessors to pure distributed memory chips. The 48-core SCC processor reported in this paper is an intermediate case, sharing traits of message passing and shared memory architectures. The hardware has been described elsewhere. In this paper, we describe the programmer's view of this chip. In particular we describe RCCE: the native message passing model created for the SCC processor.
Conference: Supercomputing Conference - SC , pp. 1-11, 2010
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    • ...Intel provides a customized programming library for the SCC, called RCCE [3][4]...
    • ...More details about the curve progression of the shown bandwidth graphs and their correlation with cache level sizes can be found in [4]...

    Carsten Clauss, et al. Evaluation and improvements of programming models for the Intel SCC ma...

    • ...Examples of such emerging multi-core platforms are the Intels SCC [1] and STs Platform 2012 [2]...
    • ...<{[REF]}>REFERENCES [1] A. Di Biagio and G. Agosta...

    C. Silvano, et al. Invited paper: Parallel programming and run-time resource management f...

    • ...These address spaces and how they are used in programming the chip are described in [4]...
    • ...MPB addresses apply to any physical address range marked with the MPBT tag. See [4] for details...
    • ...As described in [4], software must explicitly maintain coherence between cores with regard to data placed in the MPB...
    • ...This instruction is sufficient to implement a consistency protocol for the data in the MPB with respect to multiple cores in the processor [4]...
    • ...As described in [4], an instruction is invoked inside the RCCE_put() function to invalidate all L1 cache lines that map to the MPB...
    • ...This applies to the messages sent in the NAS Parallel Benchmarks LU and BT [4,14], as well as to those passed in High Performance Linpack [15] (the subject of investigation of the next section)...
    • ...Network latencies are well understood [4] and follow the expected pattern of approximately 4 cycles per hop across the network...

    Rob F. van der Wijngaart, et al. Lightweight communications on Intel's single-chip cloud computer proce...

    • ...In addition, MPI’s influence can be seen in recently proposed message passing notations such as the Multicore Communications API [25] and the RCCE library [24]...

    Stephen F. Siegel, et al. Formal Analysis of Message Passing - (Invited Talk)

    • ...The Single-Chip Cloud Computer (SCC) experimental processor [3], [4] is a 48-core ’concept vehicle’ created by Intel Labs as a platform for many-core software research...
    • ...Intel Labs provides a library called RCCE (pronounced ”rocky”) [5], [4]...
    • ...Flags are implemented in two alternative ways, cf. [4]:...

    Matthias Korch, et al. Memory-Intensive Applications on a Many-Core Processor

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