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A Dynamic Reconfigurable MRAM based FPGA

A Dynamic Reconfigurable MRAM based FPGA,Lionel Torres,Yoann Guillemenet,Syed Zahid Ahmed

A Dynamic Reconfigurable MRAM based FPGA   (Citations: 2)
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    • ...Thanks to the small cell area and 3D integration of MRAM, multicontext can be easily implemented, which allows dynamical and runtime reconfiguration methods [24, 31, 39]...
    • ...Figure 6 describes the general architecture of the Tile, also the TAS-MRAM based logic elements like Run-Time LUT, Multi-Context LUT and Flip-Flop are described in detail in [39]...
    • ...In Figure 8, a 19x19 MRAM FPGA array is depicted; in the [39] more details are presented...

    Weisheng Zhaoet al. Design of MRAM based logic circuits and its applications

    • ...In consequence, a differential potential is generated at the boundary of the latch (Vmin and Vmax) unbalancing it. The restore operation phase takes less than 1 ns to be performed and the necessary power for this operation is inferior to 0.1 pJ per bit [24]...

    Luís Vitório Cargniniet al. Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Ba...

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