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A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library

A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library,10.1109/ISCAS.2010.5537815,Youngmin Park,David D. Wentzloff

A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library   (Citations: 2)
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This paper presents a synthesizable cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (PAR) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of PAR mismatch is characterized in the post-layout simulation and utilized to achieve 1ps TDC resolution. The TDC was designed in a 65nm CMOS process, and occupies 0.001mm2.
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