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A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library

A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library,10.1109/ISCAS.2010.5537815,Youngmin Park,David D. Wentzloff

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A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library (Citations: 2)


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This paper presents a synthesizable cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (PAR) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of PAR mismatch is characterized in the post-layout simulation and utilized to achieve 1ps TDC resolution. The TDC was designed in a 65nm CMOS process, and occupies 0.001mm2.

Conference: IEEE International Symposium on Circuits and Systems - ISCAS , pp. 3561-3564, 2010

DOI: 10.1109/ISCAS.2010.5537815

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- ...In this paper, we focus on a TDC specifically for ADPLLs, and propose a cyclic Vernier structure which is synthesized from a standard cell library [17]...
Youngmin Park, et al. A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Libra...
- ...In Section III, this paper introduces a calibration scheme that accounts for systematic mismatch from automatic layout of the DCO, which is applicable for the ADPLL in closed-loop operation, and is also applied to the DCO-based TDC [14]...
- ...We use a DCO-based Vernier TDC to measure the phase difference between Fref and Fdiv, and the details of the TDC architecture and operation are described in [14]...
Youngmin Park, et al. An all-digital PLL synthesized from a digital standard cell library in...

A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution (Citations: 21)

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Conference: Symposium on VLSI Circuits - VLSIC , 2008

A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy (Citations: 15)

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Journal: IEEE Transactions on Nuclear Science - IEEE TRANS NUCL SCI , vol. 54, no. 2, pp. 294-302, 2007

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Keywords (5)

A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library,10.1109/ISCAS.2010.5537815,Youngmin Park,David D. Wentzloff

Citation Context (2)

Youngmin Park, et al. A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Libra...

Youngmin Park, et al. An all-digital PLL synthesized from a digital standard cell library in...

References (10)

Digitally Assisted Analog Circuits (Citations: 39)

A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS (Citations: 54)

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS (Citations: 83)

A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution (Citations: 21)

A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy (Citations: 15)

Citations (2)

A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS


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