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A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS

A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS,10.1109/VLSISOC.2010.5642669,Joachim Neves Rodrigues,Omer Can Akgun,Viktor Öwall

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A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS (Citations: 4)


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This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate energy efficiency of standard-cell based designs, over several CMOS technology generations, from 180 to 65 nm, operated in the sub-threshold domain. The simulation results indicate a 65 nm low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65 nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250 mV. At the energy minimum voltage of 320 mV the circuit dissipates 0.88 pJ per sample at a clock rate of 20 kHz.

Conference: Very Large Scale Integration - VLSI , pp. 253-258, 2010

DOI: 10.1109/VLSISOC.2010.5642669

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- ...energy per clock cycle with respect to supply voltage gives the so called Energy Minimum Voltage (EMV) point [8]...
S. M. Yasser Sherazi, et al. Design exploration of a 65 nm Sub-VT CMOS digital decimation filter ch...
- ...As an alternative to variation-tolerant full-custom circuit design, [4]–[6] promote the design of sub- circuits based on conventional standard-cell libraries...
- ...Furthermore, accuracy of the model is validated by measurements in [6] and [20]...
Pascal Meinerzhagen, et al. Benchmarking of Standard-Cell Based Memories in the Sub$V_{\rm T}$ Dom...
- ...Energy dissipation is calculated under the assumption that the designs operate at critical path speed, which gives an Energy Minimum Voltage (EMV) point [9]...
S. M. Yasser Sherazi, et al. Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS...

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Keywords (3)

A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS,10.1109/VLSISOC.2010.5642669,Joachim Neves Rodrigues,Omer Can Akgun,Viktor Öwall

Citation Context (3)

S. M. Yasser Sherazi, et al. Design exploration of a 65 nm Sub-VT CMOS digital decimation filter ch...

Pascal Meinerzhagen, et al. Benchmarking of Standard-Cell Based Memories in the Sub$V_{\rm T}$ Dom...

S. M. Yasser Sherazi, et al. Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS...

References (10)

The evolution of pacemakers (Citations: 13)

A very low-power CMOS mixed-signal IC for implantable pacemaker applications (Citations: 55)

Modeling and sizing for minimum energy operation in subthreshold circuits (Citations: 127)

A 2.6 µW sub-threshold mixed-signal ECG SoC (Citations: 23)

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM (Citations: 47)

Citations (4)

Synthesis strategies for sub-VT systems

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Benchmarking of Standard-Cell Based Memories in the Sub$V_{\rm T}$ Domain in 65-nm CMOS Technology

Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters


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