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Automatic Pipelining From Transactional Datapath Specifications

Automatic Pipelining From Transactional Datapath Specifications,10.1109/TCAD.2010.2088950,IEEE Transactions on Computer-aided Design of Integrated Cir

Automatic Pipelining From Transactional Datapath Specifications   (Citations: 2)
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    • ...To address this, prior works (e.g., [11][13][15]) have presented design frameworks that can be used to automatically synthesize custom pipelined processor implementations (usually at the register transfer level) from a precise high-level specification...
    • ...In this paper, we present an effort to integrate formal verification with the T-piper high-level pipeline synthesis framework [13]...
    • ...Note that we chose to use this simple example for the sake of brevity. Details on Tspec can be found in [13]...
    • ...More details on T-piper synthesis are available at [13]...
    • ...Existing high-level design frameworks (e.g., [11][13][15]) provides correct-by-construction property, but do not have integrated formal verification to ensure the correctness of the output implementation that it generates...

    Eriko Nurvitadhiet al. Integrating formal verification and high-level processor pipeline synt...

    • ...The work which has the most similar goals to ours is, however, by Nurvitadhi et al. [28]...
    • ...E.g., our approach does not need manually implemented “read-enable” and “write-enable” signals, nor do we impose the restrictions of [28] on the structure of the write interface of the pipeline...

    Georg Hoffereket al. Controller synthesis for pipelined circuits using uninterpreted functi...

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