Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip,10.1109/TCAD.2010.2065990,IEEE Transactions on Computer-

• ...A major step in the process is to determine the assignment of the switches of the topology onto the layers of the 3D IC. In most 3D technologies, Through Silicon Vias (TSVs) are used to establish the vertical links across layers [5]...

M. Pawan Kumar, et al. A Method for Integrating Network-on-Chip Topologies with 3D ICs