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Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,10.1109/DATE.2008.4484813,Jie Zhang,Nishant P. Patil,Subhasish Mitra

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits   (Citations: 12)
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Metallic carbon nanotubes (CNTs) create source-drain shorts in carbon nanotube field effect transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variation. There is no known CNT growth technique that guarantees 0% metallic CNTs. Therefore, metallic CNT removal techniques are necessary. Unfortunately, such removal techniques alone are imperfect and insufficient. This paper demonstrates the necessity for co-optimization of processing techniques for metallic CNT removal together with CNFET-based circuit design. We present a probabilistic CNFET circuit model which forms the basis for such co-optimization, and use the model to derive design and processing guidelines that enable design of CNFET-based digital circuits with practical constraints on leakage, noise margin and delay variations. These guidelines are essential for designing robust metallic- carbon-nanotube-tolerant digital circuits.
Conference: Design, Automation, and Test in Europe - DATE , pp. 1009-1014, 2008
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