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Pattern-based behavior synthesis for FPGA resource reduction

Pattern-based behavior synthesis for FPGA resource reduction,10.1145/1344671.1344688,Jason Cong,Wei Jiang

Pattern-based behavior synthesis for FPGA resource reduction   (Citations: 12)
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Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for desi gn opti- mizations. In this paper we present a general pattern-based be- havior synthesis framework which can efficiently extract si milar structures in programs. Our approach is very scalable in benefit of advanced pruning techniques that include locality sensitive hashing and characteristic vectors. The similarity of structures i s captured by a mismatch-tolerant metric: graph edit distance. The edit dis- tance between two graphs is the minimum number of vertex/edge insertion, deletion, substitution operations to transfor m one graph into the other. Graph edit distance can naturally handle var ious pro- gram variations such as bit-width, structure, and port vari ations. In addition, we apply our pattern-based synthesis system to FPGA re- source optimization with the observation that multiplexors are par- ticularly expensive on FPGA platforms. Considering knowledge of discovered patterns, the resource binding step can intelli gently gen- erate the data-path to reduce interconnect costs. Experiments show our approach can, on average, reduce the total area by about 20% with 7% latency overhead on the Xilinx Virtex-4 FPGAs, compared to the traditional behavior synthesis flow.
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    • ...In [16], a pattern-based approach for resource sharing is proposed...

    Jason Conget al. High-Level Synthesis for FPGAs: From Prototyping to Deployment

    • ...design automation, e.g., J. Cong et al. applied the edit distance measure to FPGA resource optimization [10]...

    Xiaoyu Shiet al. Enhancement of incremental design for FPGAs using circuit similarity

    • ...In this paper, we leverage the recently proposed pattern matching technique [3] to identify the patterns in the mapped circuit netlist, and then use this information to share hardware resources among the same pattern instances...
    • ...We apply the recent pattern matching technique in [3] to find patterns in the circuit netlist...
    • ...The pattern matching algorithm in [3] has two phases: pattern enumeration and pattern selection...

    Jason Conget al. Accelerating Monte Carlo based SSTA using FPGA

    • ...Recently, these approaches have been applied to solve problems in various domains, such as data mining, biochemistry, and behavioral synthesis [4, 8, 9, 10, 11, 13]...
    • ...Recently, a pattern-based behavioral synthesis framework was proposed in [4]...
    • ...In our approach, a signature called two-level feature vector is introduced for each CDFG subgraph, based on the work in [4]...
    • ...However, the features discussed in [4] are constricted to data flow graph...
    • ...As discussed in [4], DFG nodes with multiple outputs will also be counted as ε node...
    • ...Theorem 1 from [4] tells us that given an edit distance limit ldist, the maximal number of possible DFG feature misses between two CDFG subgraphs is 4 *ldist...
    • ...Our work is compared to a traditional behavioral synthesis flow [6, 7], and the DFG pattern-based synthesis result in [4]...
    • ...technique [4], and with CDFG pattern-based technique, respectively...
    • ...For most test cases, CDFG pattern extraction outperforms work in [4], which can not efficiently deal with sharing at the basic block level...

    Jason Conget al. A generalized control-flow-aware pattern recognition algorithm for beh...

    • ...To cope with this problem, [7] proposed a regularity extraction method in which patterns are classified by locality-sensitive hashing, and presented a framework for whole processing of HLS...

    Yui Ogawaet al. A datapath classification method for FPGA-based scientific application...

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