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Mapping for better than worst-case delays in LUT-based FPGA designs

Mapping for better than worst-case delays in LUT-based FPGA designs,10.1145/1344671.1344681,Kirill Minkovich,Jason Cong

Mapping for better than worst-case delays in LUT-based FPGA designs   (Citations: 4)
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Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experienced, forcing designers to reduce performance requirements in order to reserve larger margins. Better than worst-case design can be used to address the variability problem, as well as breaking the performance limit set by the worst-case delay in the conventional design style, even without the consideration of delay variation. In this paper we will present a novel methodology for measuring and optimizing the performance of circuits to operate with the clock period smaller than the worst-case delay. We also develop a novel technology mapping algorithm that optimizes circuits under such a metric. Using our novel mapping algorithm named BTWMap (Better Than Worst-case Mapper) and its area-optimized version named BTWMap+area, we are able to improve the overall circuit latency by 13% and 11%, respectively.
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    • ...Also related, BTWMap [8] is a gate-mapping algorithm (part of the logic synthesis flow) that uses a switching activity profile to minimize the common-case delay...

    Brian Greskampet al. Blueshift: Designing processors for timing speculation from the ground...

    • ...The only study known to us is the one we presented in [4] where only the FPGA map algorithm was modified with a much higher area overhead and only applied to favorable circuits...
    • ...The first and simplest method was to pre-compute the original cost function from [4] (equation (3) listed below) for each node and use it as the tie breaker...
    • ...Similar to the work in [4] for FPGAs, we found that a good tradeoff between accuracy and runtime would be to simulate 100,000 random inputs...
    • ...[4] also had multiple iterations of simulating a small subset of values and using that information for mapping...
    • ...However, with real delays used in standard libraries, the switching vectors grew 15X (as compared to [4]), thus making any reduction of switching in a single interval not very significant...
    • ...To further reduce area, we took the concept of target delay from [4] and applied it to library mapping...

    Jason Conget al. Logic synthesis for better than worst-case designs

    • ...As discussed in [7], different inputs into the same gate will cause different levels of switching, potentially resulting in varied propagation delays...
    • ...Using this idea, a “stallable finite state machine (FSM) architecture” was proposed in [7], applying the ideas of Razor to a general synchronous circuit controlled by a FSM...

    Jason Conget al. A variation-tolerant scheduler for better than worst-case behavioral s...

    • ...BTWMap [37] is a general design tool that optimizes common-case performance without...

    BRIAN L. GRESKAMP. IMPROVING PER-THREAD PERFORMANCE ON CMPS THROUGH TIMING SPECULATION

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