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Entry control in network-on-chip for memory power reduction

Entry control in network-on-chip for memory power reduction,10.1145/1393921.1393967,Dongwook Lee,Sungjoo Yoo,Kiyoung Choi

Entry control in network-on-chip for memory power reduction   (Citations: 2)
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As high-end mobile embedded systems become data-intensive, the off-chip memory is becoming a major contributor to the total energy consumption. Especially, high-end mobile chips accommodate dedicated hardware blocks, e.g., codec and D graphics IP's, required for both performance and power consumption reasons. Those IP's usually do not have a large shared memory on chip. Thus, they communicate with each other via the off-chip DDR memory increasing off-chip memory accesses, which increases memory energy consumption during read/write operations. In this paper, we present a method of reducing memory energy consumption during read/write operations. It aims at minimizing the number of row opens and closes, which are the major source of energy consumption during read/write operations. The basic idea is to apply network entry control to prioritize consecutive open row memory accesses. The experimental results show up to 35% reduction in memory energy consumption with an industrial strength multimedia mobile SoC.
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    • ...tRRD is the minimum latency (e.g., 7.5ns) between two RAS (row activation) commands while tFAW (four active bank window) limits the number of RAS commands within the time interval of tFAW to four...
    • ...Especially, RAS commands for row activation is power hungry [7][8][9]...
    • ...However, the same peak power constraints as those of the traditional single channel DRAM, e.g., tRRD=7.5ns, tFAW=37.5ns, are still applied to the four channels...
    • ...Section 6 reports experimental results. Section 7 concludes the paper...
    • ...Figure 7 shows a 7x7 mesh architecture used in our experiments...
    • ...Table 2 gives the summary of architectural details. Figure 7 A 7x7 mesh architecture...
    • ...For instance, all cores denoted with ‘A’ access memory controller MC1 in Figure 7. We utilize two types of memory traffic: synthetic traffics and benchmark programs...

    Dongki Kimet al. A quantitative analysis of performance benefits of 3D die stacking on ...

    • ...1) Improve the control logic to minimize the number of row opens and closes, and lower the energy consumption during read/write operations [1]...

    Wei Geet al. The Design and Implementation of DDR PHY Static Low-Power Optimization...

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