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Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures,10.1016/j.sysarc.2007.01.002,Journal of

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures   (Citations: 6)
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In this contribution the concept of functional- level power analysis (FLPA) for power estimation of programmable processors is extended in order to model embedded as well as heterogeneous processor architectures featuring different embedded processor cores. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like, e.g. processing unit, clock network, internal memory, etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional-level and instruction-level (FLPA/ILPA) model in order to achieve a good modeling accuracy. In order to show the applicability of this approach even a heterogeneous processor architecture (OMAP5912) featuring an ARM926EJ-S core and a C55x DSP core has been modeled using the hybrid FLPA/ILPA technique described before. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders or classical benchmark suits. Estimated power figures for the inspected tasks are compared to physically measured values for both inspected processor architectures. A resulting maximum estimation error of 9% for the ARM940T and less than 4% for the OMAP5912 is achieved.
Journal: Journal of Systems Architecture - JSA , vol. 53, no. 10, pp. 689-702, 2007
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    • ...In [3], a hybrid FLPA and instruction-level microprocessor power estimation approach is proposed...

    Peter van Stralenet al. A High-level Microprocessor Power Modeling Technique Based on Event Si...

    • ...In this paper, we describe the application of the hybrid FLPA/ILPA model [2] to estimate the power consumption of different software versions for the LEON2 processor implemented on a Xilinx Virtex-II type FPGA...
    • ...Both FLPA and ILPA can be combined to a hybrid model as described in [2]...
    • ...Also, it is in the range of similar models for hardcore processors [2]...

    Peter Zipfet al. A Power Estimation Model for an FPGA-based Softcore Processor

    • ...The powermodelisbasedontheconcept ofso-called hybrid functional level/instructio n level poweranalysis (FLPA/ILPA) [3]whichhasbeensuccessfully applied tovarious processor architectures before...
    • ...The comparison ofestimated andmeasured values yields a maximumerror ofabout 6%andanaverage error ofabout 3% forthepowerconsumption...
    • ...Itcanbeseenthat byusing fourthreads ontheMPCore architecture anaverage efficiency gain of1.8(average speedup 3.4,average powerincrease 1.9) couldbeachieved...
    • ...The highest speedups andefficiency gains canbeachieved for highly regular algorithms like block matching (see chapter IV), filtering or imagetransformations (speedups 3.7-3.9, efficiency 1.8-2.2) whichfeature regular inner loops which canbeadvantageously parallelized...
    • ...The highest speedups andefficiency gains canbeachieved for highly regular algorithms like block matching (see chapter IV), filtering or imagetransformations (speedups 3.7-3.9, efficiency 1.8-2.2) whichfeature regular inner loops which canbeadvantageously parallelized...

    Holger Blumeet al. Performance and Power Analysis of Parallelized Implementations on an M...

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