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On-Chip Interconnection Networks of the TRIPS Chip

On-Chip Interconnection Networks of the TRIPS Chip,10.1109/MM.2007.90,IEEE Micro,Paul Gratz,Changkyu Kim,Karthikeyan Sankaralingam,Heather Hanson,Prem

On-Chip Interconnection Networks of the TRIPS Chip   (Citations: 28)
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Journal: IEEE Micro - MICRO , vol. 27, no. 5, pp. 41-50, 2007
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    • ...VCs can increase delay in router’s critical path due to extra arbitrations, thus it potentially affects the cycle time or pipeline depth of the router [20]...

    Faizal Arya Sammanet al. New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Vi...

    • ...Most of the NoCs such as Nostrum [10], Tile64 [11], TRIPS [12], Teraflops [13], and SCC [14] use a mesh topology...
    • ...The TRIPS NoC [12] contains two data networks, the OPN and the OCN, in which the logic areas of the OCN and OPN routers are 1.10 mm and 0.43 mm , respectively by using 130-nm technology...

    Faizal Arya Sammanet al. Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-o...

    • ...For core counts of several tens to even hundreds, Network-on-Chip (NoC) research prototypes like MIT’s RAW [2], UT Austin’s TRIPS [3], and Intel’s TeraFLOPS [4] have adopted packet-switched mesh topologies because they are scalable and provide a tile-based, homogeneous network architecture that simplifies the interconnect design and verification...
    • ...The primary contributers to NoC power are the buffers (31% in RAW [2], 35% in TRIPS [3], 22% in TeraFLOPS [4]), which are typically built out of SRAM or register files; the crossbar switches (30% in RAW [2], 33% in TRIPS [3], 15% in TeraFLOPS [4]); and the corecore links (39% in RAW [2], 31% in TRIPS [3], 17% in...
    • ...The primary contributers to NoC power are the buffers (31% in RAW [2], 35% in TRIPS [3], 22% in TeraFLOPS [4]), which are typically built out of SRAM or register files; the crossbar switches (30% in RAW [2], 33% in TRIPS [3], 15% in TeraFLOPS [4]); and the corecore links (39% in RAW [2], 31% in TRIPS [3], 17% in...
    • ...The primary contributers to NoC power are the buffers (31% in RAW [2], 35% in TRIPS [3], 22% in TeraFLOPS [4]), which are typically built out of SRAM or register files; the crossbar switches (30% in RAW [2], 33% in TRIPS [3], 15% in TeraFLOPS [4]); and the corecore links (39% in RAW [2], 31% in TRIPS [3], 17% in...
    • ...These are modeled similar to previous NoC prototypes like the TRIPS memory network [3] and Intel’s TeraFLOPS [4]...
    • ...2 The baseline router used for all comparisons was modeled similar to [4], [3] and is described in Section II-A...
    • ...Characteristic Intel TeraFLOPS [4] UT TRIPS [3] Baseline⋆...
    • ...MIT’s RAW [2], UT Austin’s TRIPS [3], and Intel’s...

    Tushar Krishnaet al. SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip ...

    • ...2D mesh interconnection network has been widely used in many prototype chips such as Intel 80core Teraflop, Tilera 64-core and TRIPS [2] [3] [4]...

    Shubo Qiet al. A high performance router with dynamic buffer allocation for on-chip i...

    • ...2D mesh interconnection network has been widely used in many prototype chips such as Intel 80-core Teraflop [2], Tilera 64-core [4] and TRIPS [3]...

    Shubo Qiet al. A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network

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