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Accelerating Sequential Applications on CMPs Using Core Spilling

Accelerating Sequential Applications on CMPs Using Core Spilling,10.1109/TPDS.2007.1085,IEEE Transactions on Parallel and Distributed Systems,Jason Co

Accelerating Sequential Applications on CMPs Using Core Spilling   (Citations: 4)
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Chip multiprocessors (CMPs) provide a scalable means of exploiting thread-level parallelism for multitasking or multithreaded applications. However, single-threaded applications will have difficulty dynamically leveraging the statically partitioned resources in a CMP. Such sequential applications may be difficult to statically decompose into threads or may simply be a legacy code where recompilation is not possible or cost-effective. We present a novel approach to dynamically accelerate the performance of sequential application(s) on multiple cores. Execution is allowed to spill from one core to another when resources on one core have been exhausted. We propose two techniques to enable low-overhead migration between cores: prespilling and locality-based filtering. We develop and analyze an arbitration mechanism to intelligently allocate cores among a set of sequential applications on a CMP. On average, core spilling on an eight-core CMP can accelerate single-threaded performance by 35 percent. We further explore an eight- core CMP running a multiple application workload composed of the entire SPEC 2000 benchmark suite in various combinations and arrival times. Using core spilling to accelerate the current set of running applications in cases where there are idle cores, we achieve up to a 40 percent improvement in performance.
Journal: IEEE Transactions on Parallel and Distributed Systems - TPDS , vol. 18, no. 8, pp. 1094-1107, 2007
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    • ...Various methods and algorithms have been proposed for the energy saving of a processor, mostly focusing on Dynamic Voltage Scaling (DVS) [5-7] and lowering power dissipation in the part of cache hierarchy [8-15]...
    • ...While some work [8, 9] focuses on a low-cost setassociative cache organization, the tag reduction technique [10-15] has received more attention in the literature because it can save energy of caches significantly...

    Long Zhenget al. I-Cache Tag Reduction for Low Power Chip Multiprocessor

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