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Fine grain reconfigurable architectures

Fine grain reconfigurable architectures,10.1109/FPL.2008.4629956,Josef Angermeier,Mateusz Majer,Jürgen Teich,Lars Braun,T. Schwalb,Philipp Graf,Michae

Fine grain reconfigurable architectures  
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Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechelehttp://academic.research.microsoft.com/io.ashx?type=5&id=4708362&selfId1=0&selfId2=0&maxNumber=12&query=
In this booth on fine grain reconfigurable architectures, several research groups demonstrate their joint work on operating concepts for managing dynamic and partial reconfiguration, visualization of bitstreams and routing, presenting an application applying dynamic reconfiguration for video engines as well as work on minimization of reconfiguration data. Unique is that all the above four projects present their work using the same reconfigurable FPGA-based fabric called Erlangen slot machine that has also been built within one project just the purpose of experimenting with dynamic fine grain reconfiguration as an interdisciplinary platform.
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