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Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy,10.1109/HPCA.2009.4798261,Niti Madan,Li Zhao,Naveen Muralimanohar

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy   (Citations: 14)
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Abstract Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this pa- per, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize horizontal communication,of cache data. We then propose a heterogeneous recongur,able cache design that takes advantage of the high density of DRAM and the superior power/delay characteristics of SRAM to efciently meet the working set demands,of each individual core. Finally, we analyze the communication patterns for such a processor and show that a tree topology is an ideal t that signicantly reduces the power and la- tency requirements of the on-chip network. The above pro- posals are synergistic: each proposal is made,more com- pelling because of its combination,with the other innova- tions described in this paper. The proposed recongur,able cache model improves performance,by up to 19% along with 48% savings in network power. Keywords: multi-core processors, cache and memory hierarchy, non-uniform cache architecture (NUCA), page coloring, on-chip networks, SRAM/DRAM cache recong- uration.
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